SWRZ149 july   2023 IWRL1432

ADVANCE INFORMATION  

  1.   1
  2. 1Introduction
  3. 2Device Nomenclature
  4. 3Device Markings
  5. 4Advisory to Silicon Variant / Revision Map
  6. 5Known Design Exceptions to Functional Specifications
    1. 5.1  ANA #51
    2. 5.2  ANA #52
    3. 5.3  DIG #1
    4. 5.4  DIG #2
    5. 5.5  DIG #3
    6. 5.6  DIG #4
    7. 5.7  DIG #6
    8. 5.8  DIG #7
    9. 5.9  DIG #8
    10. 5.10 DIG #9
    11. 5.11 DIG #10
  7. 6Trademarks
  8.   Revision History

5.10 DIG #9

TOP_IO_MUX register space not accessible from RS232 for debug purposes

Revision(s) Affected

IWRL1432ES1.1

Details

RS232 is not able to write TOP_IO_MUX registers unless the space is programmed for user mode access.

Workaround

It is recommended to use the following sequence:

  1. From Processor or DAP : Unlock TOP_IO_MUX registers (by programming LPRADAR:TOP_IO_MUX:IOCFGKICK0 = 83E7 0B13h and LPRADAR:TOP_IO_MUX:IOCFGKICK1 = 95A4 F1E0h )

  2. From Processor or DAP : Write to TOP_IO_MUX registers, LPRADAR:TOP_IO_MUX:USERMODEEN should be set to 0xADADADAD

  3. Now TOP_IO_MUX registers can be accessed from RS232.

The below table shows the Register Addresses for above workaround.

Bits

Name

Address

0:31

LPRADAR:TOP_IO_MUX:IOCFGKICK0

0x5A000068

0:31

LPRADAR:TOP_IO_MUX:IOCFGKICK0x5A00006C

0:31

LPRADAR:TOP_IO_MUX:USERMODEEN0x5A000060