TIDT359 October   2023

 

  1.   1
  2.   Description
  3.   Features
  4.   Applications
  5. 1Test Prerequisites
    1. 1.1 Voltage and Current Requirements
    2. 1.2 Dimensions
  6. 2Testing and Results
    1. 2.1 Efficiency Graphs
    2. 2.2 Efficiency Data
    3. 2.3 Thermal Images
    4. 2.4 Bode Plots
  7. 3Waveforms
    1. 3.1 Switching
    2. 3.2 Output Voltage Ripple
    3. 3.3 Input Voltage Ripple
    4. 3.4 Load Transients
    5. 3.5 Start-Up Sequence
    6. 3.6 Voltage Supervisor
    7. 3.7 Watchdog

3.7 Watchdog

The watchdog timer behavior is shown in the following figures. The selected window watchdog is between 1.85 ms and 11.0 ms (typical values).


GUID-20230922-SS0I-PV7W-SQV1-QFJV37GWHGBP-low.jpg
The watchdog is disabled (SET1 = LOW) until the first pulse on the input signal (WDI) occurs. After that, the watchdog is enabled via the flip flop (SET1 = HIGH). The watchdog does not output any errors since the WDI period is inside the allowed time window.
Figure 3-11 Watchdog at Start-Up (CH1: WDI at 5.0-ms Period, CH2: WDO, CH4: SET1)

GUID-20230925-SS0I-TQSJ-Z6RJ-PR9K5DGV9Q9L-low.jpg
The watchdog is disabled (SET1 = LOW) until the first pulse on the input signal (WDI) occurs. After that, the watchdog is enabled via the flip flop (SET1 = HIGH). The watchdog outputs an error since the input signal period is outside the allowed time window. This resets the flip flop (SET1 = LOW), and the cycle starts again.
Figure 3-12 Watchdog at Start-Up (CH1: WDI at 20.0-ms Period, CH2: WDO, CH4: SET1)