TIDU470A September   2014  – January 2026

 

  1.   1
  2.   Description
  3.   Resources
  4.   Features
  5.   Applications
  6.   6
  7. 1 Key System Specifications
  8. 2 System Description
  9. 3 Block Diagram
    1. 3.1 Highlighted Products
      1. 3.1.1 DRV81646
      2. 3.1.2 ISO6441 and ISO6421
      3. 3.1.3 LM5009
      4. 3.1.4 TLC5927
  10. 4 System Design Theory
    1. 4.1 Low-Side Driver Selection
    2. 4.2 Thermal Management
    3. 4.3 Switch Off an Inductive Load
    4. 4.4 Switching Light Bulbs
  11. 5 Getting Started Hardware
    1. 5.1 Serial Peripheral Interface (SPI)
    2. 5.2 Fault Signal
    3. 5.3 Power Supply
    4. 5.4 Output and Field Power Connector
  12. 6 Getting Started Firmware
    1. 6.1 Data Bits
    2. 6.2 GPIO for SPI
  13. 7 Test Setup
    1. 7.1 Output Current Capability
    2. 7.2 Rise and Fall Times, Propagation Delay
  14. 8 Test Data
  15. 9 Design Files
    1. 9.1 Schematics
    2. 9.2 Bill of Materials
    3. 9.3 PCB Layout
      1. 9.3.1 Layer Plots
      2. 9.3.2 Layout Recommendations
    4. 9.4 Altium Project
    5. 9.5 Gerber Files
    6. 9.6 Assembly Drawings
    7. 9.7 Software Files
  16. 10References
  17. 11About the Author
  18. 12Revision History

8 Test Data

Table 8-1 Test Results
SYMBOLPARAMETERCONDITIONSSPECIFICATIONMEAS.UNIT
MINTYPMAX
VINInput voltageNormal operation10243324.5V
IINInput currentNormal operation-1550(1)14mA
VLOADLoad supply voltageNormal operation0244424.5V
ILOADLoad currentPer channel
TA = 60°C		-500600-(2)mA
Per channel
TA = 25°C		-7001000-(2)mA
PLOSSPower loss per channelRL = 48Ω, VLOAD = 24V, TA = 25°C-200--(2)mW
fSWSwitching frequencyResistive load10001000Hz
Inductive load,
0.1H all channels		10-(2)Hz
tRISELoad voltage rise time
10% .. 90%		RL = 48Ω, VLOAD = 24V, TA = 25°C-600-550ns
tFALLLoad voltage fall time
90% .. 10%		RL = 48Ω, VLOAD = 24V, TA = 25°C-120-125ns
tPDPropagation Delay (latch to output change)RL = 48Ω, VLOAD = 24V, TA = 25°C60150200165ns
IPEAKPeak current (1ms)2.33.8-(2)A
PINDInductive power for each group of channels(3)0.5-(2)J/s
(1) Depends on number of LEDs on and communication activity
(2) Based on calculations derived from DRV8804 datasheet. DRV81646 provides improved performance and lower temperatures.
(3) Outputs Y0 to Y3 are one group and outputs Y4 to Y7 are one group

In Figure 8-1 and Figure 8-2, channel 3 (purple) is connected to the /CS0 signal of the host connector and triggers on the rising edge. This edge causes the data to transfer to the outputs Y0 to Y7 and is therefore best suited to capture the output transitions (channel 4, green) and the timings for the propagation delay measurement. The fall time is dominated by the switching speed of the output transistor in the driver. Due to the open drain configuration, the rise time results from the RC combination formed by the 10nF capacitor connected to the switch output in the reference design, the driver output capacitance and the 48Ω load resistor at the output.

TIDA-00236 Fall TimeFigure 8-1 Fall Time
TIDA-00236 Rise TimeFigure 8-3 Rise Time
TIDA-00236 tPD Falling EdgeFigure 8-2 tPD Falling Edge
TIDA-00236 tPD Rising EdgeFigure 8-4 tPD Rising Edge