TIDUCU8A september   2022  – may 2023

 

  1.   1
  2.   Description
  3.   Resources
  4.   Features
  5.   Applications
  6.   6
  7. 1System Description
  8. 2System Overview
    1. 2.1 Block Diagram
    2. 2.2 Design Considerations
      1. 2.2.1 Framehandler
  9. 3Hardware, Software, Testing Requirements, and Test Results
    1. 3.1 Hardware Requirements
    2. 3.2 Test Setup
    3. 3.3 Test Results
      1. 3.3.1 Power Supply Inrush Tests (TCM_PHYL_INTF_ISIRM)
      2. 3.3.2 Interface Wake-Up Voltages (TCM_PHYL_INTF_IQWUH and TCM_PHYL_INTF_IQWUHL)
      3. 3.3.3 Current Sink
      4. 3.3.4 Timing Tests
  10. 4Design and Documentation Support
    1. 4.1 Design Files
      1. 4.1.1 Schematics
      2. 4.1.2 BOM
    2. 4.2 Tools and Software
    3. 4.3 Documentation Support
    4. 4.4 Support Resources
    5. 4.5 Trademarks
  11. 5Revision History

Timing Tests

Further testing was done in terms of timing, especially on the capability of a cycle time of 400 µs and the timing jitter during this communication. For this test the BOOSTXL-IOLINKM-8 is combined with the AM243x LaunchPad, and the example from the MCU+ SDK is compiled and loaded. Figure 3-8 with infinite persistence shows a cycle time of about 412 µs and no visible jitter in this configuration.

GUID-20220324-SS0I-SWRG-PWTL-MKLBLZRP8WKZ-low.pngFigure 3-8 CQ Line Communication

Figure 3-9 shows the timing to be about 417 µs, well within the range allowed by the standard. Here also, the answer time of the connected device can be seen.

GUID-20220324-SS0I-7794-QC19-2CBCFJFG1X6B-low.pngFigure 3-9 Master Cycle Timing

Figure 3-10 shows a zoomed in view of the second communication cycle on the CQ line. Trigger is set to trigger on one cycle and delay until the next one. This allows to look at the cycle to cycle jitter. With infinite persistence a jitter of about 50 ns gets visible. Compared to the rise and fall times, as well as the cycle timing, this is neglectable and does not degrade the system performance.

GUID-20220324-SS0I-FX6M-2HN7-CHZKGGXCN666-low.pngFigure 3-10 Master Cycle Jitter