TIDUDT0 September   2022

 

  1.   Description
  2.   Resources
  3.   Features
  4.   Applications
  5.   5
  6. 1System Description
    1. 1.1 Key System Specification
      1. 1.1.1 Intel® Stratix® 10 Power Tree Example
      2. 1.1.2 Intel® Agilex™ Power Tree Example
      3. 1.1.3 Xilinx Versal™ Power Tree Example
      4. 1.1.4 Xilinx Virtex-7® Power Tree Example
  7. 2System Overview
    1. 2.1 Block Diagram
    2. 2.2 Design Considerations
    3. 2.3 Highlighted Products
      1. 2.3.1 TPS53688
      2. 2.3.2 TPS650861
      3. 2.3.3 TPSM5D1806
  8. 3Hardware, Software, Testing Requirements, and Test Results
    1. 3.1 Hardware Requirements
    2. 3.2 Test Setup
      1. 3.2.1 TPS53688 Programming Setup
      2. 3.2.2 TPS53688 Transient Test Setup
      3. 3.2.3 TPS650861 Programming Setup
      4. 3.2.4 TPS650861 and TPSM5D1806 Transient Test Setup
    3. 3.3 Test Results
      1. 3.3.1 Efficiency Results
      2. 3.3.2 Transient Results
        1. 3.3.2.1 TPS53688 Transient Results
        2. 3.3.2.2 TPS650861 Transient Results
        3. 3.3.2.3 TPSM5D1806 Transient Results
  9. 4Design and Documentation Support
    1. 4.1 Design Files
      1. 4.1.1 Schematics
      2. 4.1.2 BOM
    2. 4.2 Tools and Software
    3. 4.3 Documentation Support
    4. 4.4 Support Resources
    5. 4.5 Trademarks
  10. 5About the Author

3.3.2.2 TPS650861 Transient Results

GUID-20220609-SS0I-H7ZV-CJVK-R8CFT3GF93M6-low.png Figure 3-16 TPS650861 Buck 1 Transient 0.9 V, 20 A
GUID-20220609-SS0I-HT2X-XCMW-WJWXT1MXPG22-low.png Figure 3-17 TPS650861 Buck 2 Transient 1.8 V, 20 A
GUID-20220609-SS0I-45LN-TWBS-DXCMDWK2HH4F-low.png Figure 3-18 TPS650861 Buck 6 Transient 1.2 V, 20 A
GUID-20220609-SS0I-TQSX-PGG0-J6DNSNCQNPSQ-low.png Figure 3-19 TPS650861 Buck 3 Transient 1.8 V, 3 A
GUID-20220609-SS0I-PTLS-DFZG-ZCSTRB2TNZHW-low.png Figure 3-20 TPS650861 Buck 4 Transient 2.5 V, 3 A
GUID-20220609-SS0I-T40J-J8GK-T6SZTQML39X7-low.png Figure 3-21 TPS650861 Buck 5 Transient 1.2 V, 3 A