TIDUF61 May   2024

 

  1.   1
  2.   Description
  3.   Resources
  4.   Features
  5.   Applications
  6.   6
  7. 1System Description
    1. 1.1 Key System Specifications
  8. 2System Overview
    1. 2.1 Block Diagram
    2. 2.2 Highlighted Products
      1. 2.2.1 TLV9002-Q1
      2. 2.2.2 TLV9034-Q1
      3. 2.2.3 TPS7B69-Q1
      4. 2.2.4 SN74HCS08-Q1
      5. 2.2.5 SN74HCS86-Q1
    3. 2.3 System Design Theory
      1. 2.3.1 TIDA-0020069 Operation
        1. 2.3.1.1 Constant Current Source
          1. 2.3.1.1.1 Design Goals
          2. 2.3.1.1.2 Design Description
          3. 2.3.1.1.3 Design Notes
          4. 2.3.1.1.4 Design Steps
        2. 2.3.1.2 Current Sensing
          1. 2.3.1.2.1 Design Goals
          2. 2.3.1.2.2 Design Description
          3. 2.3.1.2.3 Design Steps
        3. 2.3.1.3 Load Connections and Clamps
        4. 2.3.1.4 Modified Window Comparator
        5. 2.3.1.5 Digital Logic Gates
      2. 2.3.2 Status Indication
        1. 2.3.2.1 Normal Operation (Closed Connection) State
        2. 2.3.2.2 Open Connection State
        3. 2.3.2.3 Short-to-Battery State
        4. 2.3.2.4 Short-to-Ground State
  9. 3Hardware, Testing Requirements, and Test Results
    1. 3.1 Hardware Requirements
    2. 3.2 Test Setup
    3. 3.3 Test Results
      1. 3.3.1 Normal Operation (Closed Connection) Test Results
      2. 3.3.2 Open Connection Test Results
      3. 3.3.3 Short-to-Battery Test Results
      4. 3.3.4 Short-to-Ground Test Results
      5. 3.3.5 Disable (Shutdown) Test Results
  10. 4Design Files
    1. 4.1 Schematics
    2. 4.2 Bill of Materials
    3. 4.3 PCB Layout Recommendations
      1. 4.3.1 Layout Prints
    4. 4.4 Altium Project
    5. 4.5 Gerber Files
    6. 4.6 Assembly Drawings
  11. 5Tools and Software
  12. 6Documentation Support
  13. 7Support Resources
  14. 8Trademarks
  15. 9About the Author

3.3.5 Disable (Shutdown) Test Results

Figure 3-11 shows the TIDA-020069 board configured in the disable (shutdown) mode. In this state, the disable voltage at connector J4 is pulled to a logic level high. The amplifier is disabled when this signal is active high. The output current of the constant current source is decreased by a factor of 100. The voltage drop across the HVIL load is also decreased by a factor of 100 in disable mode, and the voltage ranges of HVIL-Send and HVIL-Return appear similar to the short-to-battery failure mode. This optional input signal allows for a manual override that can force the HVIL design into a failure state until the overall system is ready to continue HVIL readings.

The Short to Battery LED indicator is turned on in Figure 3-11, as expected for this state. This verifies the logical interpretation of the HVIL-Send and HVIL-Return voltages in this state.

TIDA-020069 Disable (Shutdown) Test Results Figure 3-11 Disable (Shutdown) Test Results