This section describes the software requirements for the minimal setup. The Software development kit (SDK) for Jacinto™ 7 processors is used to control and monitor the Ethernet PHY on this reference design (shown in Figure 4-1) during testing.

The automotive Ethernet PHY driver needs to be added to the Linux SDK for the Jacinto™ 7 processor to be able to identify the Ethernet PHY. See the How to Integrate Linux Driver Into Your System application note.

The Linux Device Tree overlay for this specific board with the PHY configured for PHY address 15 is shown in the following code block for Jacinto™ 7 SDK v10. For other SDK versions, see the SDK documentation.

/dts-v1/;
/plugin/;

#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/phy/phy.h>
#include <dt-bindings/phy/phy-cadence.h>
#include "k3-pinctrl.h"
#include "k3-serdes.h"

&{/} {
	aliases {
		ethernet2 = "/bus@100000/ethernet@c000000/ethernet-ports/port@2";
	};
};

&cpsw0 {
	status = "okay";
};

&cpsw0_port2 {
	status = "okay";
	phy-handle = <&cpsw9g_phy15>;
	phy-mode = "sgmii";
	mac-address = [00 00 00 00 00 00];
	phys = <&cpsw0_phy_gmii_sel 2>;
};

&cpsw9g_mdio {
	status = "okay";
	pinctrl-names = "default";
	pinctrl-0 = <&mdio0_pins_default>;
	reset-gpios = <&exp2 17 GPIO_ACTIVE_LOW>;
	reset-post-delay-us = <120000>;
	#address-cells = <1>;
	#size-cells = <0>;

	cpsw9g_phy15: ethernet-phy@15 {
		reg = <15>;
	};
};

&exp2 {
	qsgmii-line-hog {
		gpio-hog;
		gpios = <16 GPIO_ACTIVE_HIGH>;
		output-low;
		line-name = "qsgmii-pwrdn-line";
	};
};

&main_pmx0 {
	mdio0_pins_default: mdio0-pins-default {
		pinctrl-single,pins = <
			J721E_IOPAD(0x1bc, PIN_OUTPUT, 0) /* (V24) MDIO0_MDC */
			J721E_IOPAD(0x1b8, PIN_INPUT, 0) /* (V26) MDIO0_MDIO */
		>;
	};
};

&serdes_ln_ctrl {
	idle-states = <J721E_SERDES0_LANE0_PCIE0_LANE0>, <J721E_SERDES0_LANE1_QSGMII_LANE2>,
		      <J721E_SERDES1_LANE0_PCIE1_LANE0>, <J721E_SERDES1_LANE1_PCIE1_LANE1>,
		      <J721E_SERDES2_LANE0_PCIE2_LANE0>, <J721E_SERDES2_LANE1_PCIE2_LANE1>,
		      <J721E_SERDES3_LANE0_USB3_0_SWAP>, <J721E_SERDES3_LANE1_USB3_0>,
		      <J721E_SERDES4_LANE0_EDP_LANE0>, <J721E_SERDES4_LANE1_EDP_LANE1>,
		      <J721E_SERDES4_LANE2_EDP_LANE2>, <J721E_SERDES4_LANE3_EDP_LANE3>;
};

&serdes_wiz0 {
	status = "okay";
};

&serdes0 {
	status = "okay";

	assigned-clocks = <&serdes0 CDNS_SIERRA_PLL_CMNLC>, <&serdes0 CDNS_SIERRA_PLL_CMNLC1>;
	assigned-clock-parents = <&wiz0_pll1_refclk>, <&wiz0_pll1_refclk>;
	#address-cells = <1>;
	#size-cells = <0>;

	serdes0_qsgmii_link: phy@1 {
		reg = <1>;
		cdns,num-lanes = <1>;
		#phy-cells = <0>;
		cdns,phy-type = <PHY_TYPE_SGMII>;
		resets = <&serdes_wiz0 2>;
	};
};

In addition to adding the PHY driver, adjusting the Device Tree, the following needs to be done, to enable the SGMII interface:

Inside the file: SDK_Install_Directory/board-support/ti-u-boot-<version>/configs/j721e_evm_a72_defconfig

Comment out the following two lines with # as shown below:

# CONFIG_PHY_CADENCE_SIERRA=y 
# CONFIG_PHY_J721E_WIZ=y 

After that, build u-boot using the top level make command:

make u-boot

Copy the build binaries u-boot.img and tispl.bin to the boot partition of the SD-card.

sudo cp SDK_Install_Directory/board-support/ti-u-boot-x/build/a72/u-boot.img /media/$USER/boot
sudo cp SDK_Install_Directory/board-support/ti-u-boot-x/build/a72/tispl.bin /media/$USER/boot

Change the linked firmware of r5f0_0-fw with the following command:

ln -sfn /usr/lib/firmware/ti-ipc/j721e/ipc_echo_test_mcu2_0_release_strip.xer5f /lib/firmware/j7-main-r5f0_0-fw

With the board powered up, use the following terminal command to confirm the PHY address (phy[x]) and eth port (eth[y]).:

dmesg | grep mdio

davinci_mdio c000f00.mdio: phy[15]: device c000f00.mdio:0f, driver TI DP83TC817CS2.0
am65-cpsw-nuss c000000.ethernet eth1: PHY [c000f00.mdio:0f] driver [TI DP83TC817CS2.0] (irq=POLL)