TIDUFB4A December   2024  – July 2026

1.   1
2.   Description
3.   Resources
4.   Features
5.   Applications
6.   6
7. 1System Description
   1. 1.1 Terminology
   2. 1.2 Key System Specifications
8. 2System Overview
   1. 2.1 Block Diagram
   2. 2.2 Design Considerations
   3. 2.3 Highlighted Products - AM243x subsystems
      1. 2.3.1 Control Board - SORTE_G Controller Interface
      2. 2.3.2 Control Board – SDFM Interface
      3. 2.3.3 Control Board - EPWM Interface
      4. 2.3.4 Control Board - ICSSG_PRU PWM Interface
      5. 2.3.5 Control Board - ICSSG_PRU IEP Timer
      6. 2.3.6 Control Board – FOC Loop Control
      7. 2.3.7 Position Board – SORTE_G Device Interface
      8. 2.3.8 Position Board – PRU_EQEP Interface
      9. 2.3.9 Position Board – SoC EQEP Module Interface
9. 3System Design Theory
   1. 3.1 Position Board – System Initialization
   2. 3.2 Position Board – Interrupts
   3. 3.3 Control Board – System Initialization
   4. 3.4 Control Board – Interrupts
10. 4Hardware, Software, Testing Requirements, and Test Results
    1. 4.1 Hardware Requirements
       1. 4.1.1 System Demonstration Setup
    2. 4.2 Software Requirements
    3. 4.3 Test Setup and Results
       1. 4.3.1 Current Feedback – SDFM
       2. 4.3.2 Time Synchronization Between Industrial Ethernet (SORTE_G) and PWM Interface
       3. 4.3.3 FOC Loop Verification
          1. 4.3.3.1 FOC Loop Timing
          2. 4.3.3.2 FOC Loop Processing Time Verification
       4. 4.3.4 Verification for Closed-Loop Control With PI Controller
11. 5Design and Documentation Support
    1. 5.1 Design Files
       1. 5.1.1 Schematics
       2. 5.1.2 BOM
       3. 5.1.3 Layer Plots
       4. 5.1.4 Altium Project
       5. 5.1.5 Gerber Files
       6. 5.1.6 Assembly Drawings
    2. 5.2 Tools and Software
    3. 5.3 Documentation Support
    4. 5.4 Support Resources
    5. 5.5 Trademarks
12. 6About the Author
13. 7Revision History