TIDUFJ3A May   2026  – August 2026

 

  1.   1
  2.   Description
  3.   Resources
  4.   Features
  5.   Applications
  6.   6
  7. 1System Description
    1. 1.1 Key System Specifications
  8. 2System Overview
    1. 2.1 Block Diagram
    2. 2.2 Design Considerations
      1. 2.2.1 Codec Design
      2. 2.2.2 Class-D Amplifier Design
      3. 2.2.3 Power Design
    3. 2.3 Highlighted Products
      1. 2.3.1 PCMD3180-Q1
      2. 2.3.2 TAS6511-Q1
      3. 2.3.3 LMR51450-Q1
      4. 2.3.4 TLV767-Q1
  9. 3Hardware, Software, Testing Requirements, and Test Results
    1. 3.1 Hardware Requirements
    2. 3.2 Software
      1. 3.2.1 Example Script
    3. 3.3 Test Setup
    4. 3.4 Test Results
  10. 4Design and Documentation Support
    1. 4.1 Design Files
      1. 4.1.1 Schematics
      2. 4.1.2 BOM
      3. 4.1.3 PCB Layout Recommendations
    2. 4.2 Tools and Software
      1. 4.2.1 Tools
      2. 4.2.2 Software
    3. 4.3 Documentation Support
    4. 4.4 Support Resources
    5.     Trademarks
  11. 5About the Author
  12. 6Revision History

Example Script

The following I2C commands show how to set up the PCMD3180-Q1 for processing the 8-channel PDM microphone array, and the TAS6511-Q1 for audio playback.

## PCMD3180-Q1 Device Setup ##
 ################################################################
# PDM 8-channel: PDMDIN1 - Ch1 and Ch2, PDMDIN2 - Ch3 and Ch4,
# PDMDIN3 - Ch5 and Ch6, PDMDIN4 - Ch7 and Ch8
# PDMCLKx = 2.8224MHz
# FSYNC = 48kHz (Output Data Sample Rate), BCLK = 12.288MHz (BCLK#FSYNC = 256)
 ################################################################
w 98 00 00 # Select Page 0
w 98 01 01 # Software Reset
w 98 00 00 # Select Page 0
w 98 02 81 # Exit Sleep Mode
w 98 00 00 # Select Page 0
w 98 07 30 # TDM, 32-bit
w 98 0B 00 # Channel 1 to TDM slot 0
w 98 0C 01 # Channel 2 to TDM slot 1
w 98 0D 02 # Channel 3 to TDM slot 2
w 98 0E 03 # Channel 4 to TDM slot 3
w 98 0F 04 # Channel 5 to TDM slot 4
w 98 10 05 # Channel 6 to TDM slot 5
w 98 11 06 # Channel 7 to TDM slot 6
w 98 12 07 # Channel 8 to TDM slot 7
w 98 13 81 # Controller mode with MCLK = 12.288MHz
# w 98 13 01 # Replace the command above for Target Mode
w 98 14 48 # FSYNC = 48kHz, BCLK/FSYNC = 256
w 98 1F 40 # PDMCLK is 2.8224MHz or 3.072MHz
w 98 20 00 # PDMCLK Channel 1/3/5/7 latch on negative edge, Channel 2/4/6/8 latch on positive edge
w 98 21 A0 # GPIO1 configured as MCLK input
w 98 22 41 # GPO1 = PDMCLK1
w 98 23 41 # GPO2 = PDMCLK2
w 98 24 41 # GPO3 = PDMCLK3
w 98 25 41 # GPO4 = PDMCLK4
w 98 2B 45 # GPI1 = PDMDIN1, GPI2 = PDMDIN2
w 98 2C 67 # GPI3 = PDMDIN3, GPI4 = PDMDIN4
w 98 3C 40 # Enable Channel 1 as PDM input
w 98 41 40 # Enable Channel 2 as PDM input
w 98 46 40 # Enable Channel 3 as PDM input
w 98 4B 40 # Enable Channel 4 as PDM input
w 98 50 40 # Enable Channel 5 as PDM input
w 98 55 40 # Enable Channel 6 as PDM input
w 98 5A 40 # Enable Channel 7 as PDM input
w 98 5F 40 # Enable Channel 8 as PDM input
w 98 6C 20 # 1 biquad per channel
w 98 73 FF # Enable input channels 1-8
w 98 74 FF # Enable output slots 1-8
w 98 75 E0 # Enable MICBIAS, PLL, and all PDM channels
r 98 76 02 # Read device status

## TAS6511-Q1 Device Setup ##
 ################################################################
w B0 00 00 # Page switching (1st 00) to page 0 (2nd 00)
w B0 7F 00 # Change to book 0
w B0 01 19 # Device reset
w B0 00 00 # Page switching (1st 00) to page 0 (2nd 00)
w B0 7F 00 # Change to book 0
w B0 7D 11 # Enter setup mode (1 of 2)
w B0 7E FF # Enter setup mode (2 of 2)
w B0 00 01 # Page switching (00) to page 1 (01)
w B0 28 40 # Set DIG deglitch
w B0 57 01 # Enable Isense in Hi-Z
w B0 7D 00 # Exit setup mode (1 of 2)
w B0 7E 00 # Exit setup mode (2 of 2)
w B0 00 00 # Page switching (1st 00) to page 0 (2nd 00)
w B0 21 15 # TDM mode
w B0 23 0C # 32-bit word length
w B0 25 0C # 32-bit word length
w B0 61 05 # Enable SS
w B0 62 08 # SS period from 1/FSS to 8/FSS
w B0 00 00 # Page switching (1st 00) to page 0 (2nd 00)
w B0 03 40 # Set device to play mode