Introduction

In semiconductor test systems, a faster sampling rate ADC (Analog-to-Digital Converter) can provide several benefits, including:

1. Reduced noise: Faster sampling rates can reduce noise in the signal, as the ADC can capture more samples of the signal, and the ADC can average the signals to reduce noise.
2. Better detection of transient events: Transient events in a signal, such as spikes or glitches, can occur for a very short time and be missed by slower ADCs. With a wide-bandwidth and faster sampling rate ADC, these events can be captured more accurately, providing a better understanding of the signal's characteristics.
3. Improved testing speed: Faster sampling rate ADCs can also enable faster testing speeds, as the ADC can acquire and process more data per unit time.
4. Compatibility with high-speed devices: Faster and more complex devices generate signals with higher bandwidths. To accurately capture and test these signals, faster sampling rate ADCs are required.
5. Flexibility in testing multiple signals: With faster sampling rate ADCs, multiple signals can be tested at once, as the ADC can rapidly switch between signals to capture data.

All of these benefits of a high-speed ADC can help improve the accuracy and efficiency of testing electronic devices. A high-speed ADC requires a high-speed data interface with the controller of the system for transmission of digital data. This application note describes a source-synchronous data interface for high-speed data transmission from ADC to controller in semiconductor test systems.

Source-Synchronous Data Interface

The ADS9817 is an eight-channel data acquisition (DAQ) system based on a dual, simultaneous-sampling, 18-bit successive approximation register (SAR) analog-to-digital converter (ADC). The ADS981x supports 2 MSPS/channel sampling rate at every analog input channel. A high-speed digital interface supporting 1.2-V to 1.8-V operation enables the ADS9817 to be used with a variety of host controllers. Refer to Precision ADC for Measuring Analog Outputs of Parametric Measurement Unit (PMU) on precision ADC for measuring the analog outputs of parametric measurement unit (PMU) in semiconductor test.

The clock speed for 20-bit data transfer using single-edge of data clock is given by Equation 1.

The ADS9817 data sheet features a source-synchronous data interface to enable high-speed ADC interface. A source-synchronous interface is a type of interface where the data is output by the ADC synchronously with a dedicated clock signal that is transmitted along with the data. This process is in contrast to a regular serial peripheral interface (SPI), where the data is transmitted asynchronously with respect to the clock signal. The following are some advantages of source-synchronous interface over regular SPI:

1. Improved timing: Source-synchronous interface helps to mitigate timing issues, such as skew and jitter, that can cause timing violations in asynchronous interfaces like SPI. The dedicated clock output signal in a source-synchronous interface synchronizes the data and arrives at the receiver at the correct time.
2. Higher data rates: Source-synchronous interfaces can support higher data rates than regular SPI. This outcome is because synchronous interfaces can transmit data along with the clock signal, whereas SPI transmits data one bit at a time. This outcome can be particularly advantageous in high-speed communication applications.
3. Easier PCB Layout: Source-synchronous interface is generally easier to lay out on a printed circuit board (PCB) than regular SPI. This outcome is because the timing requirements are less stringent, and there are fewer interconnects to manage.
4. Easier Interface with FPGA: FPGA logic can use logic primitives like flip-flop to capture the source-synchronous data with clock. In regular SPI, the FPGA captures ADC output data with a clock locally generated by the FPGA that can result in reduced timing margin.

Figure 1-1 shows the delays associated with regular SPI that adversely impact timing margin. The serial interface clock is generated by the FPGA that propagates along the transmission distance with delay (t_{P_D}). The clock is further delayed by the input buffer (t_{IP_D}). The ADC responds with data that is delayed by the output buffer (t_{OP_D}) and the same transmission distance (t_{P_D}) before being received by the FPGA. Hence the ADC output data received by the FPGA is considerably delayed with respect to the SPI clock generated by the FPGA. This delay reduces the timing margin available to the FPGA to capture ADC data.

The ADS9817 generates the output data and data-clock as shown in Figure 1-2. There is no clock-to-data delay as both data and data-clock are generated by the ADC. Overall, source synchronous interface can offer improved performance and simpler design compared to regular SPI.