SBOA324 May   2021 OPA172 , OPA2991 , TLV9042


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Design Goals

Input CurrentAmbient light currentOutput voltageTarget BandwidthSupply

Design Description

This circuit uses an op amp configured as a transimpedance amplifier to amplify the AC signal of a photodiode (modeled by Ii and C3). The circuit rejects DC signals using a transistor to sink DC current out of the photodiode through the use of an integrator in a servo loop. The bias voltage applied to the non-inverting input prevents the output from saturating to the negative supply rail in the absence of input current.


Design Notes

  1. Use a JFET or CMOS input op amp with low-bias current to reduce DC errors.
  2. A capacitor placed in parallel with the feedback resistor will limit bandwidth, improve stability and help reduce noise.
  3. The junction capacitance of photodiode changes with reverse bias voltage which will influence the stability of the circuit.
  4. Reverse-biasing the photodiode can reduce the effects of dark current.
  5. A resistor, R3, may be needed on the output of the integrator amplifier.
  6. An emitter degeneration resistor, R4, should be used to help stabilize the BJT.
  7. Use the op amp in a linear operating region. Linear output swing is usually specified under the AOL test conditions.

Design Steps

The transfer function of the circuit is:

Vout = –Ii × R1
  1. Calculate the value of the feedback resistor, R1, to produce the desired output swing.
    R1=VoMaxVoMinIiMaxIiMin=4.5V – 0.5V10µA – (–10µA)=200kΩ
  2. Calculate the feedback capacitor to limit the signal bandwidth.
    C1=12π × R1× fp=12π × 200kΩ × 300kHz= 2.65pF ≈ 2.7pF (Standard Value)
  3. Calculate the gain bandwidth of the amplifier needed for the circuit to be stable.
    GBW =Ci+ C12π × R1× C12=23pF + 2.7pF2π × 200kΩ ×(2.7pF)2= 2.97MHz


    Ci=Cpd+Cb+Cd+Ccm= 10pF + 5pF + 4pF + 4pF = 23pF


    • Cpd: Junction capacitance of photodiode
    • Cb: Output capacitance of BJT
    • Cd: Differential input capacitance of the amplifier
    • Ccm: Common-mode input capacitance of the inverting input
  4. Set the cutoff frequency of the integrator circuit, fl, to 0.1Hz to only allow signals near DC to be subtracted from the photodiode output current. The cutoff frequency is set by R2 and C2. Select R2 as 1MΩ.
    C2=12π × R2× fl=12π × 1MΩ × 0.1Hz= 1.59µF ≈ 2.2µF (Standard Value)
  5. Select R3 as 100Ω to isolate the capacitance of the BJT from op amp and stabilize the amplifier. For more information on stability analysis, see the Design References section [2].
  6. Bias the output of the circuit by setting the input common mode voltage of the integrator circuit to mid-supply. Select R5 and R6 as 100kΩ.
    Vcm =R6R5+R6× Vcc =100kΩ100kΩ + 100kΩ× 5V = 2.5V
  7. Calculate capacitor C2 to filter the power supply and resistor noise. Set the cutoff frequency to 1Hz.
    C2=12π ×(R2|| R3) × 1Hz=12π × (100kΩ || 100kΩ) × 1Hz= 3.183µF ≈ 4.7µF

Design Simulations

DC Simulation Results


Transient Simulation Results


Integrator Open Loop Stability


TIA Stability Results


Design References

  1. See Analog Engineer's Circuit Cookbooks for TI's comprehensive circuit library.
  2. TI Precision Labs

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#Channels 1, 2, 4

1, 2, 4