SBOA324 May   2021

Design Goals

Input CurrentAmbient light currentOutput voltageTarget BandwidthSupply
IiMinIiMaxVoMinVoMaxVccVee
–10µA10µA100µA0.5V4.5V300kHz5V0V

Design Description

This circuit uses an op amp configured as a transimpedance amplifier to amplify the AC signal of a photodiode (modeled by Ii and C3). The circuit rejects DC signals using a transistor to sink DC current out of the photodiode through the use of an integrator in a servo loop. The bias voltage applied to the non-inverting input prevents the output from saturating to the negative supply rail in the absence of input current. Design Notes

1. Use a JFET or CMOS input op amp with low-bias current to reduce DC errors.
2. A capacitor placed in parallel with the feedback resistor will limit bandwidth, improve stability and help reduce noise.
3. The junction capacitance of photodiode changes with reverse bias voltage which will influence the stability of the circuit.
4. Reverse-biasing the photodiode can reduce the effects of dark current.
5. A resistor, R3, may be needed on the output of the integrator amplifier.
6. An emitter degeneration resistor, R4, should be used to help stabilize the BJT.
7. Use the op amp in a linear operating region. Linear output swing is usually specified under the AOL test conditions.

Design Steps

The transfer function of the circuit is:

1. Calculate the value of the feedback resistor, R1, to produce the desired output swing.
${\text{R}}_{1}=\frac{{V}_{\text{oMax}}–{V}_{\text{oMin}}}{{I}_{\text{iMax}}–{I}_{\text{iMin}}}=\frac{\text{4.5V – 0.5V}}{\text{10µA – (–10µA)}}=\text{200kΩ}$
2. Calculate the feedback capacitor to limit the signal bandwidth.
3. Calculate the gain bandwidth of the amplifier needed for the circuit to be stable.

Where:

${C}_{i}={C}_{\mathrm{pd}}+{C}_{b}+{C}_{d}+{C}_{\mathrm{cm}}\text{= 10pF + 5pF + 4pF + 4pF = 23pF}$

Given:

• Cpd: Junction capacitance of photodiode
• Cb: Output capacitance of BJT
• Cd: Differential input capacitance of the amplifier
• Ccm: Common-mode input capacitance of the inverting input
4. Set the cutoff frequency of the integrator circuit, fl, to 0.1Hz to only allow signals near DC to be subtracted from the photodiode output current. The cutoff frequency is set by R2 and C2. Select R2 as 1MΩ.
5. Select R3 as 100Ω to isolate the capacitance of the BJT from op amp and stabilize the amplifier. For more information on stability analysis, see the Design References section .
6. Bias the output of the circuit by setting the input common mode voltage of the integrator circuit to mid-supply. Select R5 and R6 as 100kΩ.
$\text{Vcm =}\frac{{R}_{6}}{{R}_{5}+{R}_{6}}\text{× Vcc =}\frac{\text{100kΩ}}{\text{100kΩ + 100kΩ}}\text{× 5V = 2.5V}$
7. Calculate capacitor C2 to filter the power supply and resistor noise. Set the cutoff frequency to 1Hz.
${\text{C}}_{2}\text{=}\frac{\text{1}}{\text{2π ×}{\text{(R}}_{2}{\text{|| R}}_{3}\text{) × 1Hz}}\text{=}\frac{\text{1}}{\text{2π × (100kΩ || 100kΩ) × 1Hz}}\text{= 3.183µF ≈ 4.7µF}$

Design Simulations

DC Simulation Results Transient Simulation Results  Integrator Open Loop Stability TIA Stability Results Design References

1. See Analog Engineer's Circuit Cookbooks for TI's comprehensive circuit library.
2. TI Precision Labs

Design Featured Op Amp

OPA172
Vcc±2.25V to ±18V, 4.5V to 36V
VinCM(V–) – 0.1V to (V+) – 2V
VoutRail-to-rail
Vos0.2mV
Iq1.6mA
Ib8pA
UGBW10MHz
SR10V/µs
#Channels1,2,4
www.ti.com/product/OPA172

Design Alternate Op Amps

OPA2991

TLV9042

Vss ±1.35V to ±20V, 2.7V to 40V

±0.6V to ±2.75V, 1.2V to 5.5V

VinCM Rail-to-rail Rail-to-rail
Vout Rail-to-rail Rail-to-rail
Vos 125µV

0.6mV

Iq 560µV

10uA

Ib 1pA

1pA

UGBW 4.5MHz

350kHz

SR 20V/µs

0.2V/us

#Channels 1, 2, 4

1, 2, 4

www.ti.com/product/OPA2991 www.ti.com/product/TLV9042