SDAA315 March   2026 AM2432 , AM625 , AM62A7 , AM62D-Q1 , AM62L , AM62P , AM6442

1.   1
2.   Abstract
3.   Trademarks
4. 1 Introduction
5. 2 Terminology
6. 3 PHY Tuning Algorithm
7. 4 Key Tuning Parameters
   1. 4.1 Parameter Configurations for Non-DQS PHY Tuning Algorithm
   2. 4.2 Parameter Configurations for DQS PHY Tuning Algorithm
8. 5 Prerequisites for PHY Tuning Algorithm
   1. 5.1 Hardware Requirements
      1. 5.1.1 Flash Device Preparation
      2. 5.1.2 PHY Configuration
   2. 5.2 Attack Vector
   3. 5.3 Passing vs Failing Region
   4. 5.4 Master vs Bypass Mode
      1. 5.4.1 Bypass Mode
      2. 5.4.2 Master Mode
9. 6 Need for a Newer Tuning Algorithm
   1. 6.1 Temperature Variations
10. 7 Algorithm Implementation
    1. 7.1 DQS PHY Tuning Algorithm
       1. 7.1.1 Diagonal Selection
       2. 7.1.2 Valid Read Delays Selection
       3. 7.1.3 Corner Points Identification
          1. 7.1.3.1 Corner Point Selection for Only One Read Delay Value
          2. 7.1.3.2 Corner Point Selection for Two Different Read Delay Values
       4. 7.1.4 Tuning Point Selection
    2. 7.2 Non - DQS PHY Tuning Algorithm
       1. 7.2.1 Fix Tx DLL Value
       2. 7.2.2 Find Rx Window 1
       3. 7.2.3 Find Rx Window 2
       4. 7.2.4 Choose Larger Rx Window
       5. 7.2.5 Calculate the OTP
       6. 7.2.6 Temperature Consideration
11. 8 Tuning Enhancements
    1. 8.1 Tuning Time Optimization – Skip Tuning Feature
    2. 8.2 Runtime Validation – Validate OTP
12. 9 Summary
13. 10References

Enhanced OSPI PHY Tuning Algorithm for Sitara^TM Processors on MCU+ SDK