One high-speed comparator (COMP) with 8-bit reference DAC
32-ns propagation delay
Low power mode down to <1-µA
Programmable analog
connections between ADC, OPAs, COMP, and DAC
Integrated temperature sensor
Optimized low-power modes
RUN: 71 µA/MHz (CoreMark)
STOP: 151 µA at 4 MHz and 44 µA at 32 kHz
STANDBY: 1.0 µA with
32-kHz 16-bit timer running, SRAM/registers fully retained, and 32MHz
clock wakeup in 3.2µs
SHUTDOWN: 61 nA with IO wakeup capability
Intelligent digital peripherals
3-channel DMA controller
3-channel event fabric signaling system
Four 16-bit general-purpose timers, each with two capture/compare registers supporting low-power operation in STANDBY mode, supporting a total of 8 PWM channels
Windowed watchdog timer
Enhanced communication interfaces
Two UART interfaces; one supports LIN, IrDA,
DALI, Smart Card, Manchester and both support low-power operation in
STANDBY
Two I2C interfaces; one supports FM+
(1 Mbit/s) and both support SMBus, PMBus, and wakeup from STOP
One SPI supports up to 16 Mbit/s
Clock system
Internal 4- to 32-MHz oscillator with ±1.2%
accuracy (SYSOSC)
Internal 32-kHz low-frequency oscillator with ±3%
accuracy (LFOSC)
Data integrity
Cyclic redundancy checker (CRC-16 or CRC-32)
Flexible I/O features
Up to 28 GPIOs
Two 5-V-tolerant open-drain IOs with fail-safe protection