SGUS033A February   2002  – May 2016 SMJ320C6203

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Description
  3. 3 Revision History
  4. 4 Description (continued)
  5. 5 Characteristics of the C6203 DSP
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  Recommended Operating Conditions
    3. 7.3  Thermal Information
    4. 7.4  Electrical Characteristics
    5. 7.5  Timing Requirements for CLKIN (PLL Used)
    6. 7.6  Timing Requirements for CLKIN [PLL Bypassed (x1)]
    7. 7.7  Timing Requirements for XCLKIN
    8. 7.8  Timing Requirements for Asynchronous Memory Cycles
    9. 7.9  Timing Requirements for Synchronous-Burst SRAM Cycles
    10. 7.10 Timing Requirements for Synchronous DRAM Cycles
    11. 7.11 Timing Requirements for the HOLD/HOLDA Cycles
    12. 7.12 Timing Requirements for Reset
    13. 7.13 Timing Requirements for Interrupt Response Cycles
    14. 7.14 Timing Requirements for Synchronous FIFO Interface
    15. 7.15 Timing Requirements for Asynchronous Peripheral Cycles
    16. 7.16 Timing Requirements With External Device as Bus Master
    17. 7.17 Timing Requirements With C62x as Bus Master
    18. 7.18 Timing Requirements With External Device as Asynchronous Bus Master
    19. 7.19 Timing Requirements for Expansion Bus Arbitration (Internal Arbiter Enabled)
    20. 7.20 Timing Requirements for McBSP
    21. 7.21 Timing Requirements for FSR when GSYNC = 1
    22. 7.22 Timing Requirements for McBSP as SPI Master or Slave: CLKSTP = 10b, CLKXP = 0
    23. 7.23 Timing Requirements for McBSP as SPI Master or Slave: CLKSTP = 11b, CLKXP = 0
    24. 7.24 Timing Requirements for McBSP as SPI Master or Slave: CLKSTP = 10b, CLKXP = 1
    25. 7.25 Timing Requirements for McBSP as SPI Master or Slave: CLKSTP = 11b, CLKXP = 1
    26. 7.26 Timing Requirements for Timer Inputs
    27. 7.27 Timing Requirements for JTAG Test Port
    28. 7.28 Switching Characteristics for CLKOUT2
    29. 7.29 Switching Characteristics for XFCLK
    30. 7.30 Asynchronous Memory Timing Switching Characteristics
    31. 7.31 Switching Characteristics for Synchronous-Burst SRAM Cycles
    32. 7.32 Switching Characteristics for Synchronous DRAM Cycles
    33. 7.33 Switching Characteristics for the HOLD/HOLDA Cycles
    34. 7.34 Switching Characteristics for Reset
    35. 7.35 Switching Characteristics for Interrupt Response Cycles
    36. 7.36 Switching Characteristics for Synchronous FIFO Interface
    37. 7.37 Switching Characteristics for Asynchronous Peripheral Cycles
    38. 7.38 Switching Characteristics With External Device as Bus Master
    39. 7.39 Switching Characteristics With C62x as Bus Master
    40. 7.40 Switching Characteristics With External Device as Asynchronous Bus Master
    41. 7.41 Switching Characteristics for Expansion Bus Arbitration (Internal Arbiter Enabled)
    42. 7.42 Switching Characteristics for Expansion Bus Arbitration (Internal Arbiter Disabled)
    43. 7.43 Switching Characteristics for McBSP
    44. 7.44 Switching Characteristics for McBSP as SPI Master or Slave
    45. 7.45 Switching Characteristics for McBSP as SPI Master or Slave: CLKSTP = 11b, CLKXP = 0
    46. 7.46 Switching Characteristics for McBSP as SPI Master or Slave: CLKSTP = 10b, CLKXP = 1
    47. 7.47 Switching Characteristics for McBSP as SPI Master or Slave: CLKSTP = 11b, CLKXP = 1
    48. 7.48 Switching Characteristics for DMAC Outputs
    49. 7.49 Switching Characteristics for Timer Outputs
    50. 7.50 Switching Characteristics for Power-Down Outputs
    51. 7.51 Switching Characteristics for JTAG Test Port
  8. 8 Parameter Measurement Information
    1. 8.1 Signal Transition Levels
    2. 8.2 Timing Parameters and Board Routing Analysis
  9. 9 Detailed Description
    1. 9.1 Functional Block Diagram
    2. 9.2 Feature Description
      1. 9.2.1 Signal Groups Description
      2. 9.2.2 CPU (DSP Core) Description
      3. 9.2.3 Clock PLL
    3. 9.3 Register Maps
      1. 9.3.1 Memory Map Summary
      2. 9.3.2 Peripheral Register Descriptions
      3. 9.3.3 Interrupt Sources and Interrupt Selector
  10. 10Application and Implementation
    1. 10.1 Typical Application
      1. 10.1.1 Detailed Design Procedure
  11. 11Power Supply Recommendations
    1. 11.1 Power-Supply Sequencing
    2. 11.2 System-Level Design Considerations
    3. 11.3 Power-Supply Design Considerations
  12. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 Third-Party Products Disclaimer
      2. 12.1.2 Development Support
        1. 12.1.2.1 Software Development Tools
        2. 12.1.2.2 Hardware Development Tools
      3. 12.1.3 Device and Development-Support Tool Nomenclature
    2. 12.2 Documentation Support
      1. 12.2.1 Related Documentation
    3. 12.3 Community Resources
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • GLP|429
Thermal pad, mechanical data (Package|Pins)
Orderable Information

1 Features

  • High-Performance Fixed-Point Digital Signal Processor (DSP) SMJ320C62x™
    • 5-ns Instruction Cycle Time
    • 200-MHz Clock Rate
    • Eight 32-Bit Instructions/Cycle
    • 1600 Million Instructions per Second (MIPS)
  • 429-Pin Ball Grid Array (BGA) Package (GLP Suffix)
  • VelociTI™ Advanced Very-Long-Instruction-Word (VLIW) C62x™ DSP Core
    • Eight Highly-Independent Functional Units:
      • Six Arithmetic Logic Units (ALUs) (32-/40-Bit)
      • Two 16-Bit Multipliers (32-Bit Result)
    • Load-Store Architecture With 32 32-Bit General-Purpose Registers
    • Instruction Packing Reduces Code Size
    • All Instructions Conditional
  • Instruction Set Features
    • Byte-Addressable (8-, 16-, 32-Bit Data)
    • 8-Bit Overflow Protection
    • Saturation
    • Bit-Field Extract, Set, Clear
    • Bit-Counting
    • Normalization
  • 7Mb On-Chip SRAM
    • 3Mb Internal Program/Cache (96K 32-Bit Instructions)
    • 4Mb Dual-Access Internal Data (512KB)
    • Organized as Two 256KB Blocks for Improved Concurrency
  • Flexible Phase-Locked-Loop (PLL) Clock Generator
  • 32-Bit External Memory Interface (EMIF)
    • Glueless Interface to Synchronous Memories: SDRAM or SBSRAM
    • Glueless Interface to Asynchronous Memories: SRAM and EPROM
    • 52MB Addressable External Memory Space
  • Four-Channel Bootloading Direct-Memory-Access (DMA) Controller With an Auxiliary Channel
  • 32-Bit Expansion Bus − Glueless/Low-Glue Interface to Popular PCI Bridge Chips
    • Glueless/Low-Glue Interface to Popular Synchronous or Asynchronous Microprocessor Buses
    • Master/Slave Functionality
    • Glueless Interface to Synchronous FIFOs and Asynchronous Peripherals
  • Three Multichannel Buffered Serial Ports (McBSPs)
    • Direct Interface to T1/E1, MVIP, SCSA Framers
    • ST-Bus-Switching Compatible
    • Up to 256 Channels Each
    • AC97-Compatible
    • Serial-Peripheral Interface (SPI) Compatible (Motorola®)
  • Two 32-Bit General-Purpose Timers
  • IEEE-1149.1 (JTAG(2)) Boundary-Scan-Compatible
  • 0.15-μm/5-Level Metal Process
    • CMOS Technology
  • 3.3-V I/Os, 1.5-V Internal

2 Description

The SMJ320C6203 device is part of the SMJ320C62x fixed-point DSP generation in the SMJ320C6000 DSP platform. The C62x DSP devices are based on the high-performance, advanced VelociTI VLIW architecture developed by TI, making these DSPs an excellent choice for multichannel and multifunction applications.

The SMJ320C62x DSP offers cost-effective solutions to high-performance DSP-programming challenges. The SMJ320C6203 has a performance capability of up to 1600 MIPS at a clock rate of 200 MHz. The C6203 DSP possesses the operational flexibility of high-speed controllers and the numerical capability of array processors. This processor has 32 general-purpose registers of 32-bit word length and eight highly-independent functional units.

Device Information(1)

PART NUMBER PACKAGE BODY SIZE (NOM)
SMJ320C6203 CFCBGA (429) 27.00 mm × 27.00 mm × 2.26 mm
  1. For all available packages, see the orderable addendum at the end of the data sheet.
  2. IEEE Standard 1149.1-1990 Standard-Test-Access Port and Boundary Scan Architecture.

3 Revision History

Changes from * Revision (February 2002) to A Revision

4 Description (continued)

The eight functional units provide six ALUs for a high degree of parallelism and two 16-bit multipliers for a 32-bit result. The C6203 can produce two multiply-accumulates (MACs) per cycle for a total of 400 million MACs per second (MMACS). The C6203 DSP also has application-specific hardware logic, on-chip memory, and additional on-chip peripherals. The C6203 device program memory consists of two blocks, with a 256KB block configured as memory-mapped program space, and the other 128KB block user-configurable as cache or memory-mapped program space. Data memory for the C6203 consists of two 256KB blocks of RAM.

The C6203 device has a powerful and diverse set of peripherals. The peripheral set includes three McBSPs, two general-purpose timers, a 32-bit expansion bus that offers ease of interface to synchronous or asynchronous industry-standard host bus protocols, and a glueless 32-bit EMIF capable of interfacing to SDRAM or SBSRAM and asynchronous peripherals.

The C62x devices have a complete set of development tools that includes: a new C compiler, an assembly optimizer to simplify programming and scheduling, and a Windows® debugger interface for visibility into source code execution.