Product details

DSP 1 C62x DSP MHz (Max) 200 CPU 32-/64-bit Rating Military Operating temperature range (C) -55 to 125
DSP 1 C62x DSP MHz (Max) 200 CPU 32-/64-bit Rating Military Operating temperature range (C) -55 to 125
CFCBGA (GLP) 429 729 mm² 27 x 27
  • High-Performance Fixed-Point Digital Signal
    Processor (DSP) SMJ320C62x™
    • 5-ns Instruction Cycle Time
    • 200-MHz Clock Rate
    • Eight 32-Bit Instructions/Cycle
    • 1600 Million Instructions per Second (MIPS)
  • 429-Pin Ball Grid Array (BGA) Package (GLP
    Suffix)
  • VelociTI™ Advanced Very-Long-Instruction-Word
    (VLIW) C62x DSP Core
    • Eight Highly-Independent Functional Units:
      • Six Arithmetic Logic Units (ALUs) (32-/40-
        Bit)
      • Two 16-Bit Multipliers (32-Bit Result)
    • Load-Store Architecture With 32 32-Bit
      General-Purpose Registers
    • Instruction Packing Reduces Code Size
    • All Instructions Conditional
  • Instruction Set Features
    • Byte-Addressable (8-, 16-, 32-Bit Data)
    • 8-Bit Overflow Protection
    • Saturation
    • Bit-Field Extract, Set, Clear
    • Bit-Counting
    • Normalization
  • 7Mb On-Chip SRAM
    • 3Mb Internal Program/Cache (96K 32-Bit
      Instructions)
    • 4Mb Dual-Access Internal Data (512KB)
    • Organized as Two 256KB Blocks for Improved
      Concurrency
  • Flexible Phase-Locked-Loop (PLL) Clock
    Generator
  • 32-Bit External Memory Interface (EMIF)
    • Glueless Interface to Synchronous Memories:
      SDRAM or SBSRAM
    • Glueless Interface to Asynchronous Memories:
      SRAM and EPROM
    • 52MB Addressable External Memory Space
  • Four-Channel Bootloading Direct-Memory-Access
    (DMA) Controller With an Auxiliary Channel
  • 32-Bit Expansion Bus − Glueless/Low-Glue
  • Glueless/Low-Glue Interface to Popular
    Synchronous or Asynchronous Microprocessor
    Buses
  • Master/Slave Functionality
  • Glueless Interface to Synchronous FIFOs and
    Asynchronous Peripherals
  • Three Multichannel Buffered Serial Ports
    (McBSPs)
    • Direct Interface to T1/E1, MVIP, SCSA
      Framers
    • ST-Bus-Switching Compatible
    • Up to 256 Channels Each
    • AC97-Compatible
    • Serial-Peripheral Interface (SPI) Compatible
      (Motorola®)
  • Two 32-Bit General-Purpose Timers
  • IEEE-1149.1 (JTAG(2)) Boundary-Scan-
    Compatible
  • 0.15-µm/5-Level Metal Process
    • CMOS Technology
  • 3.3-V I/Os, 1.5-V Internal

All trademarks are the property of their respective owners.

  • High-Performance Fixed-Point Digital Signal
    Processor (DSP) SMJ320C62x™
    • 5-ns Instruction Cycle Time
    • 200-MHz Clock Rate
    • Eight 32-Bit Instructions/Cycle
    • 1600 Million Instructions per Second (MIPS)
  • 429-Pin Ball Grid Array (BGA) Package (GLP
    Suffix)
  • VelociTI™ Advanced Very-Long-Instruction-Word
    (VLIW) C62x DSP Core
    • Eight Highly-Independent Functional Units:
      • Six Arithmetic Logic Units (ALUs) (32-/40-
        Bit)
      • Two 16-Bit Multipliers (32-Bit Result)
    • Load-Store Architecture With 32 32-Bit
      General-Purpose Registers
    • Instruction Packing Reduces Code Size
    • All Instructions Conditional
  • Instruction Set Features
    • Byte-Addressable (8-, 16-, 32-Bit Data)
    • 8-Bit Overflow Protection
    • Saturation
    • Bit-Field Extract, Set, Clear
    • Bit-Counting
    • Normalization
  • 7Mb On-Chip SRAM
    • 3Mb Internal Program/Cache (96K 32-Bit
      Instructions)
    • 4Mb Dual-Access Internal Data (512KB)
    • Organized as Two 256KB Blocks for Improved
      Concurrency
  • Flexible Phase-Locked-Loop (PLL) Clock
    Generator
  • 32-Bit External Memory Interface (EMIF)
    • Glueless Interface to Synchronous Memories:
      SDRAM or SBSRAM
    • Glueless Interface to Asynchronous Memories:
      SRAM and EPROM
    • 52MB Addressable External Memory Space
  • Four-Channel Bootloading Direct-Memory-Access
    (DMA) Controller With an Auxiliary Channel
  • 32-Bit Expansion Bus − Glueless/Low-Glue
  • Glueless/Low-Glue Interface to Popular
    Synchronous or Asynchronous Microprocessor
    Buses
  • Master/Slave Functionality
  • Glueless Interface to Synchronous FIFOs and
    Asynchronous Peripherals
  • Three Multichannel Buffered Serial Ports
    (McBSPs)
    • Direct Interface to T1/E1, MVIP, SCSA
      Framers
    • ST-Bus-Switching Compatible
    • Up to 256 Channels Each
    • AC97-Compatible
    • Serial-Peripheral Interface (SPI) Compatible
      (Motorola®)
  • Two 32-Bit General-Purpose Timers
  • IEEE-1149.1 (JTAG(2)) Boundary-Scan-
    Compatible
  • 0.15-µm/5-Level Metal Process
    • CMOS Technology
  • 3.3-V I/Os, 1.5-V Internal

All trademarks are the property of their respective owners.

The SMJ320C6203 device is part of the SMJ320C62x fixed-point DSP generation in the SMJ320C6000 DSP platform. The C62x DSP devices are based on the high-performance, advanced VelociTI VLIW architecture developed by TI, making these DSPs an excellent choice for multichannel and multifunction applications.

The SMJ320C62x DSP offers cost-effective solutions to high-performance DSP-programming challenges. The SMJ320C6203 has a performance capability of up to 1600 MIPS at a clock rate of 200 MHz. The C6203 DSP possesses the operational flexibility of high-speed controllers and the numerical capability of array processors. This processor has 32 general-purpose registers of 32-bit word length and eight highly-independent functional units.

The eight functional units provide six ALUs for a high degree of parallelism and two 16-bit multipliers for a 32-bit result. The C6203 can produce two multiply-accumulates (MACs) per cycle for a total of 400 million MACs per second (MMACS). The C6203 DSP also has application-specific hardware logic, on-chip memory, and additional on-chip peripherals. The C6203 device program memory consists of two blocks, with a 256KB block configured as memory-mapped program space, and the other 128KB block user-configurable as cache or memory-mapped program space. Data memory for the C6203 consists of two 256KB blocks of RAM.

The C6203 device has a powerful and diverse set of peripherals. The peripheral set includes three McBSPs, two general-purpose timers, a 32-bit expansion bus that offers ease of interface to synchronous or asynchronous industry-standard host bus protocols, and a glueless 32-bit EMIF capable of interfacing to SDRAM or SBSRAM and asynchronous peripherals.

The C62x devices have a complete set of development tools that includes: a new C compiler, an assembly optimizer to simplify programming and scheduling, and a Windows debugger interface for visibility into source code execution.

The SMJ320C6203 device is part of the SMJ320C62x fixed-point DSP generation in the SMJ320C6000 DSP platform. The C62x DSP devices are based on the high-performance, advanced VelociTI VLIW architecture developed by TI, making these DSPs an excellent choice for multichannel and multifunction applications.

The SMJ320C62x DSP offers cost-effective solutions to high-performance DSP-programming challenges. The SMJ320C6203 has a performance capability of up to 1600 MIPS at a clock rate of 200 MHz. The C6203 DSP possesses the operational flexibility of high-speed controllers and the numerical capability of array processors. This processor has 32 general-purpose registers of 32-bit word length and eight highly-independent functional units.

The eight functional units provide six ALUs for a high degree of parallelism and two 16-bit multipliers for a 32-bit result. The C6203 can produce two multiply-accumulates (MACs) per cycle for a total of 400 million MACs per second (MMACS). The C6203 DSP also has application-specific hardware logic, on-chip memory, and additional on-chip peripherals. The C6203 device program memory consists of two blocks, with a 256KB block configured as memory-mapped program space, and the other 128KB block user-configurable as cache or memory-mapped program space. Data memory for the C6203 consists of two 256KB blocks of RAM.

The C6203 device has a powerful and diverse set of peripherals. The peripheral set includes three McBSPs, two general-purpose timers, a 32-bit expansion bus that offers ease of interface to synchronous or asynchronous industry-standard host bus protocols, and a glueless 32-bit EMIF capable of interfacing to SDRAM or SBSRAM and asynchronous peripherals.

The C62x devices have a complete set of development tools that includes: a new C compiler, an assembly optimizer to simplify programming and scheduling, and a Windows debugger interface for visibility into source code execution.

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Technical documentation

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Type Title Date
* Data sheet SMJ320C6203 Fixed-Point Digital Signal Processor datasheet (Rev. A) 24 May 2016
* Errata TMS320C6203, TMS320C6203B DSPs Silicon Errata (Silicon Rev. 1.x, 2.x, 3.0, 3.1) (Rev. L) 16 Feb 2004
* SMD SMJ320C6203 SMD 5962-00510 21 Jun 2016
Technical article Bringing the next evolution of machine learning to the edge 27 Nov 2018
Technical article How quality assurance on the Processor SDK can improve software scalability 22 Aug 2018
Technical article Clove: Low-Power video solutions based on Sitara™ AM57x processors 21 Jul 2016
Technical article TI's new DSP Benchmark Site 08 Feb 2016
Application note Introduction to TMS320C6000 DSP Optimization 06 Oct 2011
More literature SMJ320C6203GLPM20/5962-0051001QXA (Rev. A) 03 May 2002
More literature Military C6000 DSPs (Rev. A) 08 May 2000

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Debug probe

TMDSEMU560V2STM-U — XDS560v2 System Trace USB Debug Probe

The XDS560v2 is the highest performance of the XDS family of debug probes and supports both the traditional JTAG standard (IEEE1149.1) and cJTAG (IEEE1149.7).  Note that it does not support serial wire debug (SWD).

All XDS debug probes support Core and System Trace in all ARM and DSP processors that (...)

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Debug probe

TMDSEMU560V2STM-UE — XDS560v2 System Trace USB & Ethernet Debug Probe

The XDS560v2 is the highest performance of the XDS family of debug probes and supports both the traditional JTAG standard (IEEE1149.1) and cJTAG (IEEE1149.7). Note that it does not support serial wire debug (SWD).

All XDS debug probes support Core and System Trace in all ARM and DSP processors that (...)

In stock
Limit: 1
Driver or library

SPRC122 — C62x/C64x Fast Run-Time Support (RTS) Library

The C62x/64x FastRTS Library is an optimized, floating-point function library for C programmers using either TMS320C62x or TMS320C64x devices. These routines are typically used in computationally intensive real-time applications where optimal execution speed is critical. By replacing the current (...)
Driver or library

SPRC265 — TMS320C6000 DSP Library (DSPLIB)

TMS320C6000 Digital Signal Processor Library (DSPLIB) is a platform-optimized DSP function library for C programmers. It includes C-callable, general-purpose signal-processing routines that are typically used in computationally intensive real-time applications. With these routines, higher (...)
Driver or library

TELECOMLIB — Telecom and Media Libraries - FAXLIB, VoLIB and AEC/AER for TMS320C64x+ and TMS320C55x Processors

Voice Library - VoLIB provides components that, together, facilitate the development of the signal processing chain for Voice over IP applications such as infrastructure, enterprise, residential gateways and IP phones. Together with optimized implementations of ITU-T voice codecs, that can be (...)
Simulation model

SMJ320C6203 GLP BSDL Model

SGUM004.ZIP (4 KB) - BSDL Model
Design tool

PROCESSORS-3P-SEARCH — Arm-based MPU, arm-based MCU and DSP third-party search tool

TI has partnered with companies to offer a wide range of software, tools, and SOMs using TI processors to accelerate your path to production. Download this search tool to quickly browse our third-party solutions and find the right third-party to meet your needs. The software, tools and modules (...)
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  • MSL rating/Peak reflow
  • MTBF/FIT estimates
  • Material content
  • Qualification summary
  • Ongoing reliability monitoring

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