SCES944 May   2022 SN74LXC1T14

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Switching Characteristics: Tpd
    7. 6.7 Switching Characteristics: TMAX
    8. 6.8 Typical Characteristics
  7. 7 Parameter Measurement Information
    1. 7.1 Load Circuit and Voltage Waveforms
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 CMOS Schmitt-Trigger Inputs with Integrated Pulldowns
        1. 8.3.1.1 Input with Integrated Dynamic Pull-Down Resistors
      2. 8.3.2 Balanced High-Drive CMOS Push-Pull Outputs
      3. 8.3.3 Partial Power Down (Ioff)
      4. 8.3.4 VCC Isolation and VCC Disconnect (Ioff-float)
      5. 8.3.5 Over-Voltage Tolerant Inputs
      6. 8.3.6 Glitch-Free Power Supply Sequencing
      7. 8.3.7 Negative Clamping Diodes
      8. 8.3.8 Fully Configurable Dual-Rail Design
      9. 8.3.9 Supports High-Speed Translation
    4. 8.4 Device Functional Modes
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 Regulatory Requirements
    2. 12.2 Documentation Support
      1. 12.2.1 Related Documentation
    3. 12.3 Receiving Notification of Documentation Updates
    4. 12.4 Support Resources
    5. 12.5 Trademarks
    6. 12.6 Electrostatic Discharge Caution
    7. 12.7 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

1 Features

  • Fully configurable dual-rail design allows each port to operate from 1.1 V to 5.5 V
  • Robust, glitch-free power supply sequencing
  • Up to 420-Mbps support for 3.3 V to 5.0 V
  • Schmitt-trigger inputs allow for slow or noisy inputs
  • Input with integrated dynamic pull-down resistors help reduce external component count
  • High drive strength (up to 32 mA at 5 V)
  • Low power consumption
    • 3-µA maximum (25°C)
    • 6-µA maximum (–40°C to 125°C)
  • VCC isolation and Vcc disconnect (Ioff-float) feature
    • If either VCC supply is < 100 mV or disconnected, all I/O's get pulled-down and then become high-impedance
  • Overvoltage tolerant inputs accept voltages up to 5.5 V regardless of supply voltage.
  • Ioff supports partial-power-down mode operation
  • Operating temperature from –40°C to +125°C
  • Latch-up performance exceeds 100 mA per JESD 78, class II
  • ESD protection exceeds JESD 22
    • 4000-V human-body model
    • 1000-V charged-device model