SLUSEZ6 December   2022 TPS536C5

PRODUCTION DATA  

  1. 1Features
  2. 2Applications
  3. 3Description
  4. 4Revision History
  5. 5Device and Documentation Support
    1. 5.1 Documentation Support
      1. 5.1.1 Related Documentation
    2. 5.2 Receiving Notification of Documentation Updates
    3. 5.3 Support Resources
    4. 5.4 Trademarks
    5. 5.5 Electrostatic Discharge Caution
    6. 5.6 Glossary
  6. 6Mechanical, Packaging, and Orderable Information
    1. 6.1 Tape and Reel Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

1 Features

  • Input voltage range: 4.5 V to 17 V
  • Output voltage range: 0.25 V to 5.5 V
  • Dual output supporting N+M ≤ 12 phases, M ≤ 6 phases
  • Native trans-inductor voltage regulator (TLVR) topology support
  • AMD® SVI3 compliant
  • Enhanced D-CAP+™ control to provide superior transient performance with excellent dynamic current sharing
  • Programmable loop compensations
  • Flexible phase-firing sequencing
  • Individual phase current calibrations and reports
  • Dynamic phase shedding with programmable current threshold for optimizing efficiency at light and heavy loads
  • Fast phase-adding for undershoot reduction
  • Driverless configuration for efficient high-frequency switching
  • Fully compatible with TI NexFET™ power stages for high-density solutions
  • Accurate, adjustable voltage positioning
  • Patented AutoBalance™ phase current balancing
  • Selectable per-phase current limit
  • PMBus™ system interface for telemetry of voltage, current, power, temperature, and fault conditions
  • 6.00 × 6.00 mm, 48-pin, 0.4 mm pitch, QFN package