SNVSA89A December   2014  – May 2015 UCC27528-Q1


  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Description (continued)
  6. Pin Configuration and Functions
  7. Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Switching Characteristics
    7. 7.7 Typical Characteristics
  8. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 VDD and Undervoltage Lockout
      2. 8.3.2 Operating Supply Current
      3. 8.3.3 Input Stage
      4. 8.3.4 Enable Function
      5. 8.3.5 Output Stage
      6. 8.3.6 Low Propagation Delays and Tightly Matched Outputs
    4. 8.4 Device Functional Modes
  9. Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. Input-to-Output Logic
        2. Enable and Disable Function
        3. VDD Bias Supply Voltage
        4. Propagation Delay
        5. Drive Current and Power Dissipation
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
    3. 11.3 Thermal Considerations
  12. 12Device and Documentation Support
    1. 12.1 Trademarks
    2. 12.2 Electrostatic Discharge Caution
    3. 12.3 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

1 Features

  • Qualified for Automotive Applications
  • AEC-Q100 Device Temperature Grade 1
    • Industry-Standard Pin Out
    • Two Independent Gate-Drive Channels
    • 5-A Peak Source and Sink Drive Current
    • CMOS Input Logic Threshold
      (Function of Supply Voltage on VDD Pins)
    • Hysteretic Logic Thresholds for High Noise Immunity
    • Independent Enable Function for Each Output
    • Inputs and Enable Pin Voltage Levels Not Restricted by VDD Pin Bias Supply Voltage
    • 4.5-V to 18-V Single Supply Range
    • Outputs Held Low During VDD UVLO (Ensures Glitch-Free Operation at Power Up and Power Down)
    • Fast Propagation Delays (17-ns Typical)
    • Fast Rise and Fall Times (7-ns and 6-ns Typical)
    • 1-ns Typical Delay Matching Between 2 Channels
    • Outputs Held in Low When Inputs Floating
    • SOIC-8 Package
    • Operating Temperature Range of –40°C to 140°C
    • –5-V Negative Voltage Handling Capability on Input Pins

    2 Applications

    • Automotive
    • Switch-Mode Power Supplies
    • DC-to-DC Converters
    • Motor Control, Solar Power
    • Gate Drive for Emerging Wideband Gap Power Devices Such as GaN

    3 Description

    The UCC27528-Q1 device is a dual-channel, high-speed, low-side gate driver capable of effectively driving MOSFET and IGBT power switches. Using a design that inherently minimizes shoot-through current, the UCC27528-Q1 device can deliver high-peak current pulses of up to 5-A source and 5-A sink into capacitive loads along with rail-to-rail drive capability and extremely small propagation delay of 17 ns (typical). In addition, the drivers feature matched internal propagation delays between the two channels which are very well suited for applications requiring dual-gate drives with critical timing, such as synchronous rectifiers. The input pin thresholds are based on CMOS logic, which is a function of the VDD supply voltage. Wide hysteresis between the high and low thresholds offers excellent noise immunity. The enable pins are based on TTL and CMOS compatible logic, independent of the VDD supply voltage.

    Device Information(1)

    UCC27528-Q1 SOIC (8) 4.90 mm × 3.91 mm
    1. For all available packages, see the orderable addendum at the end of the datasheet.

    Dual Non-Inverting Inputs

    UCC27528-Q1 fp_graphic_snvsa89.gif