SLUSF39 December   2022 UCC5880-Q1


  1. 1Features
  2. 2Applications
  3. 3Description
  4. 4Revision History
  5. 5Pin Configuration and Functions
  6. 6Device and Documentation Support
    1. 6.1 Documentation Support
      1. 6.1.1 Related Documentation
    2. 6.2 Receiving Notification of Documentation Updates
    3. 6.3 Support Resources
    4. 6.4 Trademarks
    5. 6.5 Electrostatic Discharge Caution
    6. 6.6 Glossary
  7. 7Mechanical, Packaging, and Orderable Information
    1. 7.1 Tape and Reel Information

Package Options

Mechanical Data (Package|Pins)
  • DFC|32
Thermal pad, mechanical data (Package|Pins)
Orderable Information


  • Dual output split driver with on-the-fly programmable drive strength
    • ±15-A and ±5-A drive current outputs
    • Digital input pins (GD*) for drive strength adjustment without SPI
    • 3 resistor settings R1, R2, or R1||R2
    • Integrated 4-A active Miller clamp or optional external drive for Miller clamp transistor
  • Primary and secondary side active short circuit (ASC) support
  • Internal and external supply under-voltage and over-voltage protection
  • Driver die temperature sensing and over temperature protection
  • Short-circuit protection:
    • 75-ns response time to over-current event
    • DESAT protection – selections up to 14 V
    • Shunt resistor based over-current protection
    • Configurable protection threshold values and blanking times
    • Programmable soft turnoff (STO) and two-level soft turnoff (2STO) current
  • Integrated 10-bit ADC
    • Power switch temperature, driver die temperature, DESAT pin voltage, VCC2 voltage, phase current, DC Link voltage
    • Programmable digital comparators
  • Advanced VCE/VDS clamping circuit
  • Functional Safety-Compliant
    • Developed for functional safety applications
    • Documentation available to aid ISO 26262 system design up to ASIL D
  • Integrated diagnostics:
    • Built in self-test (BIST) for protection comparators
    • Gate threshold voltage measurement for power device health monitoring
    • INP to transistor gate path integrity
    • Internal clock monitoring
    • Fault alarm and warning outputs (nFLT*)
    • ISO communication data integrity check
  • SPI based device reconfiguration, verification, supervision, and diagnosis
  • 100 kV/µs CMTI
  • Safety-related certifications:
    • 5-kVRMS isolation for 1 minute per UL1577 (planned)
    • Reinforced isolation 7070-VPK per DIN VDE 0884-11: 2017-01 (planned)
  • AEC-Q100 qualified with the following results:
    • Device temperature grade 1: -40°C to +125°C ambient operating temperature
    • Device HBM ESD classification level 2
    • Device CDM ESD classification level C4B