Product details

Sample rate (max) (Msps) 1000 Resolution (bps) 8 Number of input channels 1 Interface type Parallel LVDS Analog input BW (MHz) 1700 Features Ultra High Speed Rating Catalog Peak-to-peak input voltage range (V) 0.8 Power consumption (typ) (mW) 1430 Architecture Folding Interpolating SNR (dB) 48 ENOB (bit) 7.5 SFDR (dB) 58.5 Operating temperature range (°C) -40 to 85 Input buffer No
Sample rate (max) (Msps) 1000 Resolution (bps) 8 Number of input channels 1 Interface type Parallel LVDS Analog input BW (MHz) 1700 Features Ultra High Speed Rating Catalog Peak-to-peak input voltage range (V) 0.8 Power consumption (typ) (mW) 1430 Architecture Folding Interpolating SNR (dB) 48 ENOB (bit) 7.5 SFDR (dB) 58.5 Operating temperature range (°C) -40 to 85 Input buffer No
HLQFP (NNB) 128 484 mm² 22 x 22
  • Internal Sample-and-Hold
  • Single +1.9V ±0.1V Operation
  • Adjustable Output Levels
  • Ensured No Missing Codes
  • Low Power Standby Mode
  • Internal Sample-and-Hold
  • Single +1.9V ±0.1V Operation
  • Adjustable Output Levels
  • Ensured No Missing Codes
  • Low Power Standby Mode

The ADC081000 is a low power, high performance CMOS analog-to-digital converter that digitizes signals to 8 bits resolution at sampling rates up to 1.6 GSPS. Consuming a typical 1.4 Watts at 1 GSPS from a single 1.9 Volt supply, this device is ensured to have no missing codes over the full operating temperature range. The unique folding and interpolating architecture, the fully differential comparator design, the innovative design of the internal sample-and-hold amplifier and the self-calibration scheme enable a very flat response of all dynamic parameters beyond Nyquist, producing a high 7.5 ENOB with a 500 MHz input signal and a 1 GHz sample rate while providing a 10-18 B.E.R. Output formatting is offset binary and the LVDS digital outputs are compliant with IEEE 1596.3-1996, with the exception of a reduced common mode voltage of 0.8V.

The converter has a 1:2 demultiplexer that feeds two LVDS buses, reducing the output data rate on each bus to half the sampling rate. The data on these buses are interleaved in time to provide a 500 MHz output rate per bus and a combined output rate of 1 GSPS.

The converter typically consumes less than 10 mW in the Power Down Mode and is available in a 128-lead HLQFP and operates over the industrial (–40°C ≤ TA ≤ +85°C) temperature range.

The ADC081000 is a low power, high performance CMOS analog-to-digital converter that digitizes signals to 8 bits resolution at sampling rates up to 1.6 GSPS. Consuming a typical 1.4 Watts at 1 GSPS from a single 1.9 Volt supply, this device is ensured to have no missing codes over the full operating temperature range. The unique folding and interpolating architecture, the fully differential comparator design, the innovative design of the internal sample-and-hold amplifier and the self-calibration scheme enable a very flat response of all dynamic parameters beyond Nyquist, producing a high 7.5 ENOB with a 500 MHz input signal and a 1 GHz sample rate while providing a 10-18 B.E.R. Output formatting is offset binary and the LVDS digital outputs are compliant with IEEE 1596.3-1996, with the exception of a reduced common mode voltage of 0.8V.

The converter has a 1:2 demultiplexer that feeds two LVDS buses, reducing the output data rate on each bus to half the sampling rate. The data on these buses are interleaved in time to provide a 500 MHz output rate per bus and a combined output rate of 1 GSPS.

The converter typically consumes less than 10 mW in the Power Down Mode and is available in a 128-lead HLQFP and operates over the industrial (–40°C ≤ TA ≤ +85°C) temperature range.

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Technical documentation

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Type Title Date
* Data sheet ADC081000 High-Performance Low-Power 8-Bit 1-GSPS ADC datasheet (Rev. G) 02 May 2013
EVM User's guide AN-1615 LMH6555 Evaluation Board (Rev. A) 26 Apr 2013
Application note Generating Precision Clocks for Time- Interleaved ADCs 02 Aug 2007
White paper Interleaving ADCs for Higher Sample Rates 01 Feb 2005
White paper Ultra-High Speed ADCs Revolutionize Digital Receiver Design 01 Feb 2004

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ADC081000 IBIS Model

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