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ADC12DJ5200-SEP

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Radiation-tolerant, 30-krad, 12-bit, dual 5.2-GSPS or single 10.4-GSPS ADC

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Data sheet

ADC12DJ5200-SEP

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Data sheet Order now

Product details

Sample rate (max) (Msps) 5200, 10400 Resolution (Bits) 12 Number of input channels 1, 2 Interface type JESD204B, JESD204C Analog input BW (MHz) 7900 Features Ultra High Speed Rating Space Peak-to-peak input voltage range (V) 0.825 Power consumption (typ) (mW) 4000 Architecture Folding Interpolating SNR (dB) 55.6 ENOB (bit) 8.8 SFDR (dB) 65 Operating temperature range (°C) -55 to 125 Input buffer Yes Radiation, TID (typ) (krad) 30 Radiation, SEL (MeV·cm2/mg) 43
Sample rate (max) (Msps) 5200, 10400 Resolution (Bits) 12 Number of input channels 1, 2 Interface type JESD204B, JESD204C Analog input BW (MHz) 7900 Features Ultra High Speed Rating Space Peak-to-peak input voltage range (V) 0.825 Power consumption (typ) (mW) 4000 Architecture Folding Interpolating SNR (dB) 55.6 ENOB (bit) 8.8 SFDR (dB) 65 Operating temperature range (°C) -55 to 125 Input buffer Yes Radiation, TID (typ) (krad) 30 Radiation, SEL (MeV·cm2/mg) 43
FCCSP (ALR) 144 100 mm² 10 x 10
  • Radiation Tolerance:
    • Total Ionizing Dose (TID): 30 krad (Si)
    • Single Event Latchup (SEL): 43 MeV-cm 2/mg
    • Single Event Upset (SEU) immune registers
  • Space-enhanced plastic (space EP):
    • Meets ASTM E595 out-gassing specification
    • Vendor item drawing (VID) V62/22611
    • Temperature range: –55°C to 125°C
    • One fabrication, assembly, and test site
    • Wafer lot traceability
    • Extended product life cycle
    • Extended product change notification
  • ADC core:
    • 12-bit resolution
    • Up to 10.4 GSPS in single-channel mode
    • Up to 5.2 GSPS in dual-channel mode
  • Performance specifications:
    • Noise floor (–20 dBFS, V FS = 1 V PP-DIFF):
      • Dual-channel mode: –151.8 dBFS/Hz
      • Single-channel mode: –154.4 dBFS/Hz
    • ENOB (dual channel, F IN = 2.4 GHz): 8.6 Bits
  • Buffered analog inputs with V CMI of 0 V:
    • Analog input bandwidth (–3 dB): 8 GHz
    • Usable input frequency range: > 10 GHz
    • Full-scale input voltage (V FS, default): 0.8 V PP
  • Noiseless aperture delay (t AD) adjustment:
    • Precise sampling control: 19-fs Step
    • Simplifies synchronization and interleaving
    • Temperature and voltage invariant delays
  • Easy-to-use synchronization features:
    • Automatic SYSREF timing calibration
    • Time stamp for sample marking
  • JESD204C serial data interface:
    • Maximum lane rate: 17.16 Gbps
    • Support for 64b/66b and 8b/10b encoding
    • 8b/10b modes are JESD204B compatible
  • Optional digital down-converters (DDC):
    • Complex decimation: 4x (IBW = 0.2*F S = 2.08 GHz in DES mode, 1.04 GHz per channel in dual channel mode), 8x, 16x and 32x
    • Four independent 32-Bit NCOs per DDC
  • Peak RF Input Power (Diff): +26.5 dBm (+ 27.5 dBFS, 560x fullscale power)
  • Programmable FIR filter for equalization
  • Power consumption: 4 W
  • Power supplies: 1.1 V, 1.9 V
  • Radiation Tolerance:
    • Total Ionizing Dose (TID): 30 krad (Si)
    • Single Event Latchup (SEL): 43 MeV-cm 2/mg
    • Single Event Upset (SEU) immune registers
  • Space-enhanced plastic (space EP):
    • Meets ASTM E595 out-gassing specification
    • Vendor item drawing (VID) V62/22611
    • Temperature range: –55°C to 125°C
    • One fabrication, assembly, and test site
    • Wafer lot traceability
    • Extended product life cycle
    • Extended product change notification
  • ADC core:
    • 12-bit resolution
    • Up to 10.4 GSPS in single-channel mode
    • Up to 5.2 GSPS in dual-channel mode
  • Performance specifications:
    • Noise floor (–20 dBFS, V FS = 1 V PP-DIFF):
      • Dual-channel mode: –151.8 dBFS/Hz
      • Single-channel mode: –154.4 dBFS/Hz
    • ENOB (dual channel, F IN = 2.4 GHz): 8.6 Bits
  • Buffered analog inputs with V CMI of 0 V:
    • Analog input bandwidth (–3 dB): 8 GHz
    • Usable input frequency range: > 10 GHz
    • Full-scale input voltage (V FS, default): 0.8 V PP
  • Noiseless aperture delay (t AD) adjustment:
    • Precise sampling control: 19-fs Step
    • Simplifies synchronization and interleaving
    • Temperature and voltage invariant delays
  • Easy-to-use synchronization features:
    • Automatic SYSREF timing calibration
    • Time stamp for sample marking
  • JESD204C serial data interface:
    • Maximum lane rate: 17.16 Gbps
    • Support for 64b/66b and 8b/10b encoding
    • 8b/10b modes are JESD204B compatible
  • Optional digital down-converters (DDC):
    • Complex decimation: 4x (IBW = 0.2*F S = 2.08 GHz in DES mode, 1.04 GHz per channel in dual channel mode), 8x, 16x and 32x
    • Four independent 32-Bit NCOs per DDC
  • Peak RF Input Power (Diff): +26.5 dBm (+ 27.5 dBFS, 560x fullscale power)
  • Programmable FIR filter for equalization
  • Power consumption: 4 W
  • Power supplies: 1.1 V, 1.9 V

The ADC12DJ5200-SEP device is an RF-sampling, giga-sample, analog-to-digital converter (ADC) that can directly sample input frequencies from DC to above 10 GHz. ADC12DJ5200-SEP can be configured as a dual-channel, 5.2 GSPS ADC or single-channel, 10.4 GSPS ADC. Support of a useable input frequency range of up to 10 GHz enables direct RF sampling of L-band, S-band, C-band, and X-band for frequency agile systems.

The ADC12DJ5200-SEP uses a high-speed JESD204C output interface with up to 16 serialized lanes supporting up to 17.16 Gbps line rate. Deterministic latency and multi-device synchronization is supported through JESD204C subclass-1. The JESD204C interface can be configured to trade-off line rate and number of lanes. Both 8b/10b and 64b/66b data encoding schemes are supported. 64b/66b encoding supports forward error correction (FEC) for improved bit error rates. The interface is backwards compatible with JESD204B receivers.

Innovative synchronization features, including noiseless aperture delay adjustment and SYSREF windowing, simplify system design for multichannel applications. Optional digital down converters (DDCs) are available to provide digital conversion to base-band and to reduce the interface rate. A programmable FIR filter allows on-chip equalization.

The ADC12DJ5200-SEP device is an RF-sampling, giga-sample, analog-to-digital converter (ADC) that can directly sample input frequencies from DC to above 10 GHz. ADC12DJ5200-SEP can be configured as a dual-channel, 5.2 GSPS ADC or single-channel, 10.4 GSPS ADC. Support of a useable input frequency range of up to 10 GHz enables direct RF sampling of L-band, S-band, C-band, and X-band for frequency agile systems.

The ADC12DJ5200-SEP uses a high-speed JESD204C output interface with up to 16 serialized lanes supporting up to 17.16 Gbps line rate. Deterministic latency and multi-device synchronization is supported through JESD204C subclass-1. The JESD204C interface can be configured to trade-off line rate and number of lanes. Both 8b/10b and 64b/66b data encoding schemes are supported. 64b/66b encoding supports forward error correction (FEC) for improved bit error rates. The interface is backwards compatible with JESD204B receivers.

Innovative synchronization features, including noiseless aperture delay adjustment and SYSREF windowing, simplify system design for multichannel applications. Optional digital down converters (DDCs) are available to provide digital conversion to base-band and to reduce the interface rate. A programmable FIR filter allows on-chip equalization.
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* Data sheet ADC12DJ5200-SEP 10.4-GSPS Single-Channel or 5.2-GSPS Dual-Channel, 12-bit,RF-Sampling Analog-to-Digital Converter (ADC) datasheet PDF | HTML 12 Oct 2023

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Evaluation board

ADC12DJ5200RFEVM — ADC12DJ5200RF RF-sampling 12-bit dual 5.2-GSPS or single 10.4-GSPS ADC evaluation module

The ADC12DJ5200RF evaluation module (EVM) allows for the evaluation of device ADC12DJ5200RF. The ADC12DJ5200RF is a low-power, 12-bit, dual 5.2-GSPS/single 10.4-GSPS, RF-sampling analog-to-digital converter (ADC) with a buffered analog input, integrated digital down converter with programmable NCO (...)

User guide: PDF | HTML
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Evaluation board

TSW14J57EVM — Data capture/pattern generator: data converter EVM with 16 JESD204B lanes from 1.6-15Gbps

The TI TSW14J57 evaluation module (EVM) is a next-generation data capture card used to evaluate the performance of the new TI JESD204B family of high-speed analog-to-digital converters (ADCs), high-speed digital-to-analog converters (DACs) and analog front ends (AFEs).

Populated with an Arria® (...)

User guide: PDF | HTML
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Simulation model

ADC12DJ5200RF IBIS and IBIS-AMI Model (Rev. A)

SLVMD65A.ZIP (49879 KB) - IBIS-AMI Model
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Simulation model

ADC12DJ5200RF S-Parameter Model

SLVMDX5.ZIP (1563 KB) - S-Parameter Model
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Simulation tool

PSPICE-FOR-TI — PSpice® for TI design and simulation tool

PSpice® for TI is a design and simulation environment that helps evaluate functionality of analog circuits. This full-featured, design and simulation suite uses an analog analysis engine from Cadence®. Available at no cost, PSpice for TI includes one of the largest model libraries in the (...)
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Reference designs

TIDA-010274 — Space-grade discrete RF sampling transceiver reference design

This reference design incorporates a 10 GSPS dual digital-to-analog converter and a 5 GSPS dual analog-to-digital converter with active baluns on the RF interface supporting up through X-band. The design also incorporates a space-grade clocking daughter card and a space-grade power solution (...)
Design guide: PDF
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