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High-speed ADCs (≥10 MSPS)

ADC3583

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Single-channel, 18-bit, 65-MSPS, low-noise, ultra-low-power, low-latency ADC

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Data sheet

ADC3583

ACTIVE
Data sheet Order now

Product details

Sample rate (max) (Msps) 65 Resolution (bps) 18 Number of input channels 1 Interface type Serial LVDS Analog input BW (MHz) 900 Features High Dynamic Range, High Performance, Low Power Rating Catalog Peak-to-peak input voltage range (V) 3.2 Power consumption (typ) (mW) 119 Architecture SAR SNR (dB) 84.5 ENOB (bit) 13.7 SFDR (dB) 95 Operating temperature range (°C) -40 to 105 Input buffer No
Sample rate (max) (Msps) 65 Resolution (bps) 18 Number of input channels 1 Interface type Serial LVDS Analog input BW (MHz) 900 Features High Dynamic Range, High Performance, Low Power Rating Catalog Peak-to-peak input voltage range (V) 3.2 Power consumption (typ) (mW) 119 Architecture SAR SNR (dB) 84.5 ENOB (bit) 13.7 SFDR (dB) 95 Operating temperature range (°C) -40 to 105 Input buffer No
WQFN (RSB) 40 25 mm² 5 x 5
  • 18-bit 10/25/65 MSPS ADC
  • Noise Floor: -160 dBFS/Hz
  • Ultra Low Power with Optimized Power Scaling: 77 mW (10 MSPS) to 119 mW (65 MSPS)
  • Latency: 1 clock cycle (1-wire SLVDS)
  • Specified 18-bit, no missing codes
  • INL/DNL: ±7/ ±0.7 LSB (typ)
  • Reference: External or Internal
  • Input Bandwidth: 900 MHz (3dB)
  • Industrial Temperature Range: -40 to +105°C
  • On-chip digital filter (optional)
    • Decimation by 2, 4, 8, 16, 32
    • 32-bit NCO
  • Serial LVDS digital interface (2-, 1- and 1/2-wire)
  • Small Footprint: 40-WQFN (5x5 mm) Package
  • Spectral Performance (fIN = 1 MHz):
    • SNR: 84.5 dBFS
    • SFDR: 95 dBc HD2, HD3
    • SFDR: 100 dBFS Worst Spur
  • Spectral Performance (fIN = 20 MHz):
    • SNR: 83.5 dBFS
    • SFDR: 90 dBc HD2, HD3
    • SFDR: 95 dBFS Worst Spur
  • 18-bit 10/25/65 MSPS ADC
  • Noise Floor: -160 dBFS/Hz
  • Ultra Low Power with Optimized Power Scaling: 77 mW (10 MSPS) to 119 mW (65 MSPS)
  • Latency: 1 clock cycle (1-wire SLVDS)
  • Specified 18-bit, no missing codes
  • INL/DNL: ±7/ ±0.7 LSB (typ)
  • Reference: External or Internal
  • Input Bandwidth: 900 MHz (3dB)
  • Industrial Temperature Range: -40 to +105°C
  • On-chip digital filter (optional)
    • Decimation by 2, 4, 8, 16, 32
    • 32-bit NCO
  • Serial LVDS digital interface (2-, 1- and 1/2-wire)
  • Small Footprint: 40-WQFN (5x5 mm) Package
  • Spectral Performance (fIN = 1 MHz):
    • SNR: 84.5 dBFS
    • SFDR: 95 dBc HD2, HD3
    • SFDR: 100 dBFS Worst Spur
  • Spectral Performance (fIN = 20 MHz):
    • SNR: 83.5 dBFS
    • SFDR: 90 dBc HD2, HD3
    • SFDR: 95 dBFS Worst Spur

The ADC358x is a low noise, ultra-low power 18-bit 65 MSPS high-speed ADC family. Designed for low noise performance, it delivers a noise spectral density of -160 dBFS/Hz combined with excellent linearity and dynamic range. The ADC358x offers very good DC precision together with IF sampling support which makes it suited for a wide range of applications. High-speed control loops benefit from the short latency as low as only 1 clock cycle. The ADC consumes only 119 mW at 65 Msps and its power consumption scales well with lower sampling rates.

The ADC358x uses a serial LVDS (SLVDS) interface to output the data which minimizes the number of digital interconnects. The device supports a one-lane and two-lane option. The ADC358x is a pin to pin compatible family with different speed grades. It comes in a 40-pin QFN package (5 x 5 mm) and supports the extended industrial temperature range from -40 to +105⁰C.

The ADC358x is a low noise, ultra-low power 18-bit 65 MSPS high-speed ADC family. Designed for low noise performance, it delivers a noise spectral density of -160 dBFS/Hz combined with excellent linearity and dynamic range. The ADC358x offers very good DC precision together with IF sampling support which makes it suited for a wide range of applications. High-speed control loops benefit from the short latency as low as only 1 clock cycle. The ADC consumes only 119 mW at 65 Msps and its power consumption scales well with lower sampling rates.

The ADC358x uses a serial LVDS (SLVDS) interface to output the data which minimizes the number of digital interconnects. The device supports a one-lane and two-lane option. The ADC358x is a pin to pin compatible family with different speed grades. It comes in a 40-pin QFN package (5 x 5 mm) and supports the extended industrial temperature range from -40 to +105⁰C.
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Our ADC3660 family won the 2021 World Electronics Achievement Awards (WEAA) Product of the Year in the Amplifier/Data Conversion category.

Technical documentation

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* Data sheet ADC358x 18-bit 0.5 MSPS to 65 MSPS Low Noise Ultra-low Power ADC datasheet (Rev. A) PDF | HTML 03 Oct 2022
Analog Design Journal How to simplify AFE filtering via high‐speed ADCs with internal digital filters 10 Jan 2020

Design & development

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Evaluation board

ADC3683EVM — ADC3683 dual-channel, 18-bit, 65-MSPS, low-noise, ultra-low-power ADC evaluation module

The ADC3683 evaluation module (EVM) is a platform that demonstrates the performance of the ultra-low-power, high-linearity ADC3683. Onboard voltage regulation and flexible analog input options allow easy evaluation for many different applications.

For a complete evaluation system, use the TSW1400EVM (...)

User guide: PDF
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Evaluation board

TSW1418EVM — Data capture evaluation module

The TSW1418EVM is an entry-level FMC interface data capture card used to evaluate performances of high-speed analog-to-digital converters (ADCs). The TSW1418EVM is used to demonstrate data sheet performance specifications by capturing the sampled data over a low-voltage differential signaling (...)
User guide: PDF | HTML
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Simulation model

ADC35xx TINA-TI Reference Design

SBAM455.ZIP (158 KB) - TINA-TI Reference Design
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Simulation tool

PSPICE-FOR-TI — PSpice® for TI design and simulation tool

PSpice® for TI is a design and simulation environment that helps evaluate functionality of analog circuits. This full-featured, design and simulation suite uses an analog analysis engine from Cadence®. Available at no cost, PSpice for TI includes one of the largest model libraries in the (...)
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