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Analog-to-digital converters (ADCs)
High-speed ADCs (≥10 MSPS)

ADS5287

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Eight-Channel, 10-Bit, 40-MSPS Analog-to-Digital Converter (ADC)

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Data sheet

ADS5287

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Data sheet Order now

Product details

Sample rate (max) (Msps) 65 Resolution (Bits) 10 Number of input channels 8 Interface type Serial LVDS Analog input BW (MHz) 520 Features Low Power Rating Catalog Peak-to-peak input voltage range (V) 2 Power consumption (typ) (mW) 616 Architecture Pipeline SNR (dB) 61.7 ENOB (Bits) 9.94 SFDR (dB) 85 Operating temperature range (°C) -40 to 85 Input buffer No
Sample rate (max) (Msps) 65 Resolution (Bits) 10 Number of input channels 8 Interface type Serial LVDS Analog input BW (MHz) 520 Features Low Power Rating Catalog Peak-to-peak input voltage range (V) 2 Power consumption (typ) (mW) 616 Architecture Pipeline SNR (dB) 61.7 ENOB (Bits) 9.94 SFDR (dB) 85 Operating temperature range (°C) -40 to 85 Input buffer No
VQFN (RGC) 64 81 mm² (9 mm × 9 mm)
  • Speed and Resolution Grades:
    • 10-bit, 65MSPS
  • Power Dissipation:
    • 46mW/Channel at 30MSPS
    • 53mW/Channel at 40MSPS
    • 62mW/Channel at 50MSPS
    • 74mW/Channel at 65MSPS
  • 61.7dBFS SNR at 10MHz IF
  • Analog Input Full-Scale Range: 2VPP
  • Low-Frequency Noise Suppression Mode
  • 6dB Overload Recovery in One Clock
  • External and Internal (Trimmed) Reference
  • 3.3V Analog Supply, 1.8V Digital Supply
  • Single-Ended or Differential Clock:
    • Clock Duty Cycle Correction Circuit (DCC)
  • Programmable Digital Gain: 0dB to 12dB
  • Serialized DDR LVDS Output
  • Programmable LVDS Current Drive, Internal Termination
  • Test Patterns for Enabling Output Capture
  • Straight Offset Binary or Two’s Complement Output
  • Package Options:
    • 9mm × 9mm QFN-64
  • Speed and Resolution Grades:
    • 10-bit, 65MSPS
  • Power Dissipation:
    • 46mW/Channel at 30MSPS
    • 53mW/Channel at 40MSPS
    • 62mW/Channel at 50MSPS
    • 74mW/Channel at 65MSPS
  • 61.7dBFS SNR at 10MHz IF
  • Analog Input Full-Scale Range: 2VPP
  • Low-Frequency Noise Suppression Mode
  • 6dB Overload Recovery in One Clock
  • External and Internal (Trimmed) Reference
  • 3.3V Analog Supply, 1.8V Digital Supply
  • Single-Ended or Differential Clock:
    • Clock Duty Cycle Correction Circuit (DCC)
  • Programmable Digital Gain: 0dB to 12dB
  • Serialized DDR LVDS Output
  • Programmable LVDS Current Drive, Internal Termination
  • Test Patterns for Enabling Output Capture
  • Straight Offset Binary or Two’s Complement Output
  • Package Options:
    • 9mm × 9mm QFN-64

The ADS5287 is a high-performance, low-power, octal channel analog-to-digital converter (ADC). Available in a 9mm × 9mm QFN package, with serialized low-voltage differential signaling (LVDS) outputs and a wide variety of programmable features, the ADS5287 is highly customizable for a wide range of applications and offers an unprecedented level of system integration. An application note, XAPP774 (available at www.xilinx.com), describes how to interface the serial LVDS outputs of TI’s ADCs to Xilinx field-programmable gate arrays (FPGAs). The ADS5287 is specified over the industrial temperature range of –40°C to +85°C.

The ADS5287 is a high-performance, low-power, octal channel analog-to-digital converter (ADC). Available in a 9mm × 9mm QFN package, with serialized low-voltage differential signaling (LVDS) outputs and a wide variety of programmable features, the ADS5287 is highly customizable for a wide range of applications and offers an unprecedented level of system integration. An application note, XAPP774 (available at www.xilinx.com), describes how to interface the serial LVDS outputs of TI’s ADCs to Xilinx field-programmable gate arrays (FPGAs). The ADS5287 is specified over the industrial temperature range of –40°C to +85°C.
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Technical documentation

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Top documentation Type Title Format options Date
* Data sheet 10-Bit, Octal-Channel ADC Up to 65MSPS. datasheet (Rev. D) Jun 1, 2012
* Errata Errata to ADS528x, Datasheet Literature Number SBAS397 (Rev. B) Oct 19, 2007
Application note Design Considerations for Avoiding Timing Errors during High-Speed ADC, LVDS Dat (Rev. A) May 22, 2015
Application note Why Use Oversampling when Undersampling Can Do the Job? (Rev. A) Jul 19, 2013
Application note Understanding Serial LVDS Capture in High-Speed ADCs Jul 10, 2013
Application note Driving High-Speed ADCs: Circuit Topologies and System-Level Parameters (Rev. A) Sep 10, 2010
Application note Smart Selection of ADC/DAC Enables Better Design of Software-Defined Radio Apr 28, 2009
Application note CDCE62005 as Clock Solution for High-Speed ADCs Sep 4, 2008
Application note CDCE72010 as a Clocking Solution for High-Speed Analog-to-Digital Converters Jun 8, 2008
Application note Phase Noise Performance and Jitter Cleaning Ability of CDCE72010 Jun 2, 2008
User guide ADS528x User's Guide Jan 18, 2008
Application note QFN Layout Guidelines Jul 28, 2006

Design & development

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