The ADS5521 is a high-performance, 12-bit, 105MSPS analog-to-digital converter (ADC). To provide a complete converter solution, it includes a high-bandwidth linear sample-and-hold stage (S&H) and internal reference. Designed for applications demanding the highest speed and highest dynamic performance in little space, the ADS5521 has excellent power consumption of 571 mW at 3.3-V single-supply voltage. This allows an even higher system integration density. The provided internal reference simplifies system design requirements. Parallel CMOS-compatible output ensures seamless interfacing with common logic.
The ADS5521 is available in a 64-pin TQFP PowerPAD package and in an industrial temperature grade device.
| Top documentation | Type | Title | Format options | Date |
|---|---|---|---|---|
| * | Data sheet | 12-Bit, 105MSPS Analog-to-Digital Converter datasheet (Rev. D) | Oct 30, 2008 | |
| Application note | Design Considerations for Avoiding Timing Errors during High-Speed ADC, LVDS Dat (Rev. A) | May 22, 2015 | ||
| Application note | Why Use Oversampling when Undersampling Can Do the Job? (Rev. A) | Jul 19, 2013 | ||
| Application note | Driving High-Speed ADCs: Circuit Topologies and System-Level Parameters (Rev. A) | Sep 10, 2010 | ||
| Application note | Smart Selection of ADC/DAC Enables Better Design of Software-Defined Radio | Apr 28, 2009 | ||
| Application note | CDCE72010 as a Clocking Solution for High-Speed Analog-to-Digital Converters | Jun 8, 2008 | ||
| Application note | Phase Noise Performance and Jitter Cleaning Ability of CDCE72010 | Jun 2, 2008 | ||
| User guide | ADS5500/5541/5542/5520/5521/5522 14-&12-Bit Single Channel ADC w/LVDT1422 Output | Jul 26, 2006 | ||
| Analog design Journal | Clocking High-Speed Data Converters | Jan 18, 2005 |
For additional terms or required resources, click any title below to view the detail page where available.
The analog engineer’s calculator is designed to speed up many of the repetitive calculations that analog circuit design engineers use on a regular basis. This PC-based tool provides a graphical interface with a list of various common calculations ranging from setting operational-amplifier (...)
JITTER-SNR-CALC can be used for calculating theoretical Signal to Noise (SNR) performance of ADCs based on input frequency and clock jitter.
| Package | Pins | CAD symbols, footprints & 3D models |
|---|---|---|
| HTQFP (PAP) | 64 | Ultra Librarian |
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