ADS6125

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12-Bit, 125-MSPS Analog-to-Digital Converter (ADC)

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Product details

Parameters

Sample rate (Max) (MSPS) 125 Resolution (Bits) 12 Number of input channels 1 Interface type DDR LVDS, Parallel CMOS Analog input BW (MHz) 500 Features Low Power Rating Catalog Input range (Vp-p) 2 Power consumption (Typ) (mW) 417 Architecture Pipeline SNR (dB) 71.5 ENOB (Bits) 11.4 SFDR (dB) 90 Operating temperature range (C) -40 to 85 Input buffer No open-in-new Find other High-speed ADCs (>10MSPS)

Package | Pins | Size

VQFN (RHB) 32 25 mm² 5 x 5 open-in-new Find other High-speed ADCs (>10MSPS)

Features

  • Maximum Sample Rate: 125 MSPS
  • 12-Bit Resolution with No Missing Codes
  • 3.5 dB Coarse Gain and up to 6 dB Programmable Fine Gain for SNR/SFDR Trade-Off
  • Parallel CMOS and Double Data Rate (DDR) LVDS Output Options
  • Supports Sine, LVCMOS, LVPECL, LVDS Clock Inputs and Clock Amplitude Down to 400 mVPP
  • Clock Duty Cycle Stabilizer
  • Internal Reference with Support for External Reference
  • No External Decoupling Required for References
  • Programmable Output Clock Position and Drive Strength to Ease Data Capture
  • 3.3 V Analog and 1.8 V to 3.3 V Digital Supply
  • 32-QFN Package (5 mm × 5 mm)
  • Pin Compatible 12-Bit Family (ADS612X)
  • APPLICATIONS
    • Wireless Communications Infrastructure
    • Software Defined Radio
    • Power Amplifier Linearization
    • 802.16d/e
    • Test and Measurement Instrumentation
    • High Definition Video
    • Medical Imaging
    • Radar Systems
open-in-new Find other High-speed ADCs (>10MSPS)

Description

ADS6125/ADS6124/ADS6123/ADS6122 (ADS612X) is a family of 12-bit A/D converters with sampling frequencies up to 125 MSPS. It combines high performance and low power consumption in a compact 32 QFN package. Using an internal high bandwidth sample and hold and a low jitter clock buffer helps to achieve high SNR and high SFDR even at high input frequencies.

It features coarse and fine gain options that are used to improve SFDR performance at lower full-scale analog input ranges.

The digital data outputs are either parallel CMOS or DDR LVDS (Double Data Rate). Several features exist to ease data capture such as — controls for output clock position and output buffer drive strength, and LVDS current and internal termination programmability.

The output interface type, gain, and other functions are programmed using a 3-wire serial interface. Alternatively, some of these functions are configured using dedicated parallel pins so that the device comes up in the desired state after power-up.

ADS612X includes internal references, while eliminating the traditional reference pins and associated external decoupling. External reference mode is also supported.

The devices are specified over the industrial temperature range (-40°C to 85°C).

open-in-new Find other High-speed ADCs (>10MSPS)
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Technical documentation

= Top documentation for this product selected by TI
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Type Title Date
* Datasheet 12-BITS, 125/105/80/65 MSPS ADC WITH DDR LVDS and CMOS OUTPUTS datasheet (Rev. A) Dec. 04, 2007
Technical articles Keys to quick success using high-speed data converters Oct. 13, 2020
Technical articles How to achieve fast frequency hopping Mar. 03, 2019
Technical articles RF sampling: Learning more about latency Feb. 09, 2017
Technical articles Why phase noise matters in RF sampling converters Nov. 28, 2016
Application note Design Considerations for Avoiding Timing Errors during High-Speed ADC, LVDS Dat (Rev. A) May 22, 2015
Application note Why Use Oversampling when Undersampling Can Do the Job? (Rev. A) Jul. 19, 2013
Application note Band-Pass Filter Design Techniques for High-Speed ADCs Feb. 27, 2012
Application note Driving High-Speed ADCs: Circuit Topologies and System-Level Parameters (Rev. A) Sep. 10, 2010
Application note Smart Selection of ADC/DAC Enables Better Design of Software-Defined Radio Apr. 28, 2009
Application note CDCE62005 as Clock Solution for High-Speed ADCs Sep. 04, 2008
Application note CDCE72010 as a Clocking Solution for High-Speed Analog-to-Digital Converters Jun. 08, 2008
Application note Phase Noise Performance and Jitter Cleaning Ability of CDCE72010 Jun. 02, 2008
User guide ADS61xx and ADS61B23EVM (Rev. B) Apr. 14, 2008
Application note QFN Layout Guidelines Jul. 28, 2006

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Hardware development

EVALUATION BOARD Download
Description

The ADS6125EVM is a circuit board that allows designers to evaluate the performance of Texas Instruments‘ ADS6125 device, a low power 12-bit 125 MSPS analog to digital converter. The ADC features a configurable parallel DDR LVDS or CMOS outputs. The EVM provides a flexible environment to (...)

Features
  • Transformer coupled analog input path
  • Transformer coupled clock input path
  • Amplifier path based on the THS4509
  • Configurable parallel output modes
  • Direct connection to TSW1100 High Speed ADC Capture Card
  • Separate analog and digital supply connections
EVALUATION BOARD Download
99
Description

The TSW1405EVM is a low cost data capture circuit board used to evaluate some of Texas Instruments’ (TI) most popular high speed analog-to-digital converters (ADC).

 

The TSW1405EVM supports a high speed LVDS bus capable of providing 16-bit samples at 1.0 GSPS. The platform supports a 64k sample depth (...)

Features
  • Simple 16-bit waveform capture from many of TI’s high speed ADC EVM’s
  • Supports 64k sample depth at up to 1.0 GSPS LVDS I/O rates
  • LatticeECP3 high speed mini FPGA
  • Analyzes up to 8 channels concurrently
  • Single mini USB cable for power and data
  • Utilizes an intuitive/easy-to-use GUI package
  • Industry’s (...)
  • Software development

    SOFTWARE PROGRAMMING TOOL Download
    SUPPORT SOFTWARE Download
    High-speed data converter pro software
    DATACONVERTERPRO-SW This high-speed data converter pro GUI is a PC (Windows® XP/7 compatible) program designed to aid in evaluation of most TI high-speed data converter and analog front-end (AFE) platforms. Designed to support the entire TSW14xxx series of data-capture and pattern-generation cards (...)
    Features
    • Compatible with TSW1400, TSW1405, TSW1406 and TSW14J10, TSW14J50, TSW14J56, and TSW14J57 pattern-generation and data-capture platforms
    • Works with all TI high-speed DAC, ADC, and AFE products
    • Provides time-domain and frequency-domain analysis
    • Supports single-tone, multi-tone, and modulated (...)

    Design tools & simulation

    SIMULATION MODEL Download
    SLAC211.ZIP (915 KB) - IBIS Model
    SIMULATION TOOL Download
    PSpice® for TI design and simulation tool
    PSPICE-FOR-TI — PSpice® for TI is a design and simulation environment that helps evaluate functionality of analog circuits. This full-featured, design and simulation suite uses an analog analysis engine from Cadence®. Available at no cost, PSpice for TI includes one of the largest model libraries in the (...)
    Features
    • Leverages Cadence PSpice Technology
    • Preinstalled library with a suite of digital models to enable worst-case timing analysis
    • Dynamic updates ensure you have access to most current device models
    • Optimized for simulation speed without loss of accuracy
    • Supports simultaneous analysis of multiple products
    • (...)
    CALCULATION TOOL Download
    Analog-to-digital converter (ADC) harmonic calculator
    ADC-HARMONIC-CALC

      The ADC Harmonic Calculation tool is an excel based calculator for determining the location in frequency space of high order harmonics following Nyquist aliasing in an analog to digital converter.

      Given an ADC sample rate and the span of a signal of interest the calcultor will determine if the 2nd (...)

    CAD/CAE symbols

    Package Pins Download
    VQFN (RHB) 32 View options

    Ordering & quality

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    • Lead finish/Ball material
    • MSL rating/Peak reflow
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    • Qualification summary
    • Ongoing reliability monitoring

    Recommended products may have parameters, evaluation modules or reference designs related to this TI product.

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