The ADS6445/ADS6444/ADS6443/ADS6442 (ADS644X) is a family of high performance 14-bit 125/105/80/65 MSPS quad channel A-D converters. Serial LVDS data outputs reduce the number of interface lines, resulting in a compact 64-pin QFN package (9 mm × 9 mm) that allows for high system integration density. The device includes 3.5dB coarse gain option that can be used to improve SFDR performance with little degradation in SNR. In addition to the coarse gain, fine gain options also exist, programmable in 1dB steps up to 6dB.
The output interface is 2-wire, where each ADC data is serialized and output over two LVDS pairs. This makes it possible to halve the serial data rate (compared to a 1-wire interface) and restrict it to less than 1Gbps easing receiver design. The ADS644X also includes the traditional 1-wire interface that can be used at lower sampling frequencies.
An internal phase lock loop (PLL) multiplies the incoming ADC sampling clock to derive the bit clock. The bit clock is used to serialize the 14-bit data from each channel. In addition to the serial data streams, the frame and bit clocks are also transmitted as LVDS outputs.
The LVDS output buffers have features such as programmable LVDS currents, current doubling modes and internal termination options. These can be used to widen eye-openings and improve signal integrity, easing capture by the receiver.
The ADC channel outputs can be transmitted either as MSB or LSB first and 2s complement or straight binary.
The ADS644X has internal references, but can also support an external reference mode. The device is specified over the industrial temperature range (–40°C to 85°C).
| Top documentation | Type | Title | Format options | Date |
|---|---|---|---|---|
| * | Data sheet | QUAD CHANNEL, 14-BIT, 125/105/80/65 MSPS ADC WITH SERIAL LVDS OUTPUTS datasheet (Rev. B) | Dec 16, 2009 | |
| Application note | Design Considerations for Avoiding Timing Errors during High-Speed ADC, LVDS Dat (Rev. A) | May 22, 2015 | ||
| Application note | Why Use Oversampling when Undersampling Can Do the Job? (Rev. A) | Jul 19, 2013 | ||
| Application note | Driving High-Speed ADCs: Circuit Topologies and System-Level Parameters (Rev. A) | Sep 10, 2010 | ||
| Application note | Smart Selection of ADC/DAC Enables Better Design of Software-Defined Radio | Apr 28, 2009 | ||
| Application note | CDCE72010 as a Clocking Solution for High-Speed Analog-to-Digital Converters | Jun 8, 2008 | ||
| Application note | Phase Noise Performance and Jitter Cleaning Ability of CDCE72010 | Jun 2, 2008 | ||
| User guide | ADS6245EVM and Lattice ECP2/M Interface Demo User Guide | Jan 14, 2008 | ||
| Application note | QFN Layout Guidelines | Jul 28, 2006 |
For additional terms or required resources, click any title below to view the detail page where available.
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| Package | Pins | CAD symbols, footprints & 3D models |
|---|---|---|
| VQFN (RGC) | 64 | Ultra Librarian |
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