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Product details

Parameters

Resolution (Bits) 10 Number of input channels 1 Sample rate (Max) (kSPS) 240 Interface type SPI Architecture SAR Input type Single-Ended Multi-channel configuration Rating Catalog Reference mode Supply Input range (Max) (V) 3.6 Input range (Min) (V) 0 Features Small Size Operating temperature range (C) -40 to 85 Power consumption (Typ) (mW) 0.22 Analog voltage AVDD (Min) (V) 1.2 SNR (dB) 61.8 Analog voltage AVDD (Max) (V) 3.6 INL (Max) (+/-LSB) 0.5 Digital supply (Min) (V) 1.2 Digital supply (Max) (V) 3.6 open-in-new Find other Precision ADCs (<=10MSPS)

Package | Pins | Size

SOT-23 (DBV) 6 5 mm² 2.9 x 1.6 open-in-new Find other Precision ADCs (<=10MSPS)

Features

  • Single 1.2-V to 3.6-V Supply Operation
  • High Throughput
    • 200/240/280KSPS for 12/10/8-Bit VDD 1.6 V
    • 100/120/140KSPS for 12/10/8-Bit VDD 1.2 V
  • ±1.5LSB INL, 12-Bit NMC (ADS7866)
  • 71 dB SNR, –83 dB THD at fIN = 30 kHz (ADS7866)
  • Synchronized Conversion with SCLK
  • SPI Compatible Serial Interface
  • No Pipeline Delays
  • Low Power
    • 1.39 mW Typ at 200 KSPS, VDD = 3.6 V
    • 0.39 mW Typ at 200 KSPS, VDD = 1.6 V
    • 0.22 mW Typ at 100 KSPS, VDD = 1.2 V
  • Auto Power-Down: 8 nA Typ, 300 nA Max
  • 0 V to VDD Unipolar Input Range
  • 6-Pin SOT-23 Package
  • APPLICATIONS
    • Battery Powered Systems
    • Isolated Data Acquisition
    • Medical Instruments
    • Portable Communication
    • Portable Data Acquisition Systems
    • Automatic Test Equipment
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Description

The ADS7866/67/68 are low power, miniature, 12/10/8-bit A/D converters each with a unipolar, single-ended input. These devices can operate from a single 1.6 V to 3.6 V supply with a 200-KSPS throughput for ADS7866. In addition, these devices can maintain at least a 100-KSPS throughput with a supply as low as 1.2 V.

The sampling, conversion, and activation of digital output SDO are initiated on the falling edge of CS\. The serial clock SCLK is used for controlling the conversion rate and shifting data out of the converter. Furthermore, SCLK provides a mechanism to allow digital host processors to synchronize with the con- verter. These converters interface with micro-processors or DSPs through a high-speed SPI compatible serial interface. There are no pipeline delays associated with the device.

The minimum conversion time is determined by the frequency of the serial clock input, SCLK, while the maximum frequency of SCLK is determined by the minimum sampling time required to charge the input capacitance to 12/10/8-bit accuracy for the ADS7866/67/68, respectively. The maximum throughput is determined by how often a conversion is initiated when the minimum sampling time is met and the maximum SCLK frequency is used. Each device automatically powers down after each conversion, which allows each device to save power when the throughput is reduced while using the maximum SCLK frequency.

The converter reference is taken internally from the supply. Hence, the analog input range for these devices is 0 V to VDD.

These devices are available in a 6-pin SOT-23 package and are characterized over the industrial –40°C to 85°C temperature range.

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Technical documentation

= Top documentation for this product selected by TI
No results found. Please clear your search and try again. View all 8
Type Title Date
* Datasheet 1.2-V 12/10/8-Bit 200-KSPS/100-KSPS MICRO-POWER MINIATURE ADC s/Serial Interface datasheet Jul. 01, 2005
White papers Best of Baker's Best: Precision Data Converters -- SAR ADCs May 21, 2015
Technical articles Input considerations for SAR ADCs Jun. 20, 2014
Application notes Determining Minimum Acquisition Times for SAR ADCs, part 2 Mar. 17, 2011
Application notes Determining Minimum Acquisition Times for SAR ADCs, part 1 (Rev. A) Nov. 10, 2010
Application notes Interfacing the ADS786x to TMS470 Processors Jul. 10, 2006
User guides ADS7866EVM/ADS7867EVM/ADS7868EVM Jul. 07, 2006
Application notes Interfacing the ADS786x to the MSP430F2013 Jun. 15, 2006

Design & development

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Design tools & simulation

SIMULATION MODELS Download
SLAM154.ZIP (27 KB) - IBIS Model
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PSpice® for TI design and simulation tool
PSPICE-FOR-TI — PSpice® for TI is a design and simulation environment that helps evaluate functionality of analog circuits. This full-featured, design and simulation suite uses an analog analysis engine from Cadence®. Available at no cost, PSpice for TI includes one of the largest model libraries in the (...)
Features
  • Leverages Cadence PSpice Technology
  • Preinstalled library with a suite of digital models to enable worst-case timing analysis
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SPICE-based analog simulation program
TINA-TI TINA-TI provides all the conventional DC, transient and frequency domain analysis of SPICE and much more. TINA has extensive post-processing capability that allows you to format results the way you want them. Virtual instruments allow you to select input waveforms and probe circuit nodes voltages (...)
document-generic User guide
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Analog-to-digital converter (ADC) input driver design tool supporting multiple input types
ADC-INPUT-CALC ADC-INPUT-CALC is an online tool that provides support for designing the input buffer to an analog-to-digital converter (ADC). It offers 24 different op-amp based buffer circuits that can be used to drive an ADC input. The available topologies cover differential, single-ended and transformer-coupled (...)
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Analog engineer's calculator
ANALOG-ENGINEER-CALC — The Analog Engineer’s Calculator is designed to speed up many of the repetitive calculations that analog circuit design engineers use on a regular basis. This PC-based tool provides a graphical interface with a list of various common calculations ranging from setting op-amp gain with feedback (...)
Features
  • Expedites circuit design with analog-to-digital converters (ADCs) and digital-to-analog converters (DACs)
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SOT-23 (DBV) 6 View options

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