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The ADS8364 includes six, 16-bit, 250KHz ADCs (Analog to Digital Converters) with 6 fully differential input channels grouped into two pairs for high-speed simultaneous signal acquisition. Inputs to the sample-and-hold amplifiers are fully differential and are maintained differential to the input of the ADC. This provides excellent common-mode rejection of 80dB at 50KHz that is important in high-noise environments.
The ADS8364 offers a flexible high-speed parallel interface with a direct address mode, a cycle, and a FIFO mode. The output data for each channel is available as a 16-bit word.
| Top documentation | Type | Title | Format options | Date |
|---|---|---|---|---|
| * | Data sheet | 250kSPS, 16-Bit, 6-Channel Simultaneous Sampling A/D Converters datasheet (Rev. C) | Aug 22, 2006 | |
| Application brief | Precision ADCs in Servo Drives (Rev. A) | PDF | HTML | Oct 29, 2025 | |
| White paper | Voltage-reference impact on total harmonic distortion | Aug 1, 2016 | ||
| E-book | Best of Baker's Best: Precision Data Converters -- SAR ADCs | May 21, 2015 | ||
| Application note | Determining Minimum Acquisition Times for SAR ADCs, part 2 | Mar 17, 2011 | ||
| Application note | Determining Minimum Acquisition Times for SAR ADCs, part 1 (Rev. A) | Nov 10, 2010 | ||
| More literature | ADS8364EVM Readme Page Thank You Letter (Rev. A) | Dec 5, 2006 | ||
| Application note | Data Converters for Industrial Power Measurements (Rev. B) | Dec 9, 2005 | ||
| Application note | Interfacing the ADS8364 to the TMS320F2812 DSP | Dec 11, 2002 | ||
| Application note | Software Control of the ADS8364 | Aug 22, 2002 |
For additional terms or required resources, click any title below to view the detail page where available.
The analog engineer’s calculator is designed to speed up many of the repetitive calculations that analog circuit design engineers use on a regular basis. This PC-based tool provides a graphical interface with a list of various common calculations ranging from setting operational-amplifier (...)
JITTER-SNR-CALC can be used for calculating theoretical Signal to Noise (SNR) performance of ADCs based on input frequency and clock jitter.
| Package | Pins | CAD symbols, footprints & 3D models |
|---|---|---|
| TQFP (PAG) | 64 | Ultra Librarian |
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