Packaging information
| Package | Pins FCBGA (ALK) | 400 |
| Operating temperature range (°C) -40 to 85 |
| Package qty | Carrier 90 | JEDEC TRAY (10+1) |
Features for the AFE7700
- Quad transmitters based on direct up-conversion architecture:
- Up to 600 MHz of RF transmitted bandwidth per chain
- Quad receivers based on 0-IF down-conversion
architecture:
- Up to 200 MHz of RF received bandwidth per chain
- Feedback chain based on RF sampling ADC:
- Up to 600 MHz of RF received bandwidth
- RF frequency range: 600 MHz to 6 GHz
- Four wideband fractional-N PLL, VCO for TX and RX LO
- Dedicated integer-N PLL, VCO for data converters clock generation
- JESD204B and JESD204C SerDes interface support:
- 8 SerDes transceivers up to 29.5 Gbps
- 8b/10b and 64b/66b encoding
- 16-bit, 12-bit, 24-bit and 32-bit formatting
- Subclass 1 multi-device synchronization
- Package: 17-mm × 17-mm FCBGA, 0.8-mm pitch
Description for the AFE7700
The AFE7700 device is a high-performance, multichannel transceiver, integrating four direct up-conversion transmitter chains, four direct down-conversion receiver chains, and two wideband RF sampling digitizing auxiliary chains (feedback paths). The high dynamic range of the transmitter and receiver chains enables high performance wireless transceiver systems.
The low power dissipation and large channel integration of the AFE7700 allows the device to address the power and size constraints of multi-antenna and phased array systems. The wideband and high dynamic range feedback path can assist the Digital Pre-Distortion (DPD) of power amplifiers and IQ correction in the transmitter chain. The fast SerDes speed can reduce the number of lanes required to transfer the data in and out.
Each receiver chain of the AFE7700 includes a 28-dB range digital step attenuator (DSA), followed by a wideband passive IQ demodulator, and a baseband amplifier with integrated programmable antialiasing low pass filters, driving a continuous-time sigma-delta ADC. The RX chain can receive an instantaneous bandwidth (IBW) up to 200 MHz. Each receiver channel has two analog peak power detectors and various digital power detectors to assist an external or internal autonomous AGC control for receiver channels, and a RF overload detector for device reliability protection. The integrated QMC (quadrature mismatch compensation) algorithm is capable to continuously monitor and correct for the RX chain I and Q imbalance mismatch without the need to inject any specific signals or perform offline calibration.
Each transmitter chain includes two 14-bit, 3-Gsps IQ DACs, followed by a programmable reconstruction and DAC image rejection filter, an IQ modulator driving a wideband RF amplifier with 39-dB range gain control. The TX chain integrated QMC and LO leakage cancellation algorithms, leveraging the FB path can constantly track and correct for the TX chain IQ mismatch and LO leakage.
Each FB path is based on RF sampling architecture, and includes an input RF DSA driving a 14-bit, 3-Gsps RF ADC. The direct sampling architecture provides an inherently wideband receiver chain and simplifies the calibration of the TX chains impairments. The FB path integrates two independent NCO that allows a fast switching between two observed RF input bands.
The synthesizer section integrates four fractional-N RF PLL that can generate four different RF LO, allowing the device to support up to two different bands, each one configured as two transmitters, two receivers and one feedback paths.
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