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CD4011A

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Military 4-ch, 2-input, 3-V to 12-V NAND gates

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Data sheet

CD4011A

ACTIVE
Data sheet Order now

Product details

Technology family CD4000 Number of channels 4 Inputs per channel 2 IOL (max) (mA) 0.62 IOH (max) (mA) -0.75 Input type Standard CMOS Output type Push-Pull Features High speed (tpd 10-50ns) Data rate (max) (Mbps) 20 Rating Military Operating temperature range (°C) -55 to 125
Technology family CD4000 Number of channels 4 Inputs per channel 2 IOL (max) (mA) 0.62 IOH (max) (mA) -0.75 Input type Standard CMOS Output type Push-Pull Features High speed (tpd 10-50ns) Data rate (max) (Mbps) 20 Rating Military Operating temperature range (°C) -55 to 125
CDIP (J) 14 130.4652 mm² (— mm × — mm) CDIP_SB (JD) 14 138.9395 mm² (— mm × — mm)
  • Quiescent current specified to 15V
  • Maximum input leakage of 1 uA at 15 V (full package-temperature range)
  • 1-V noise margin (full package-temperature range)
  • Quiescent current specified to 15V
  • Maximum input leakage of 1 uA at 15 V (full package-temperature range)
  • 1-V noise margin (full package-temperature range)

The TI-CD4011A, CD4012A, and CD4023A NAND gates provide the system designer with direct implementation of the NAND function and supplement the existing family of CMOS gates

These types are supplied in 14-lead hermetic dual-in-line ceramic packages (D and F suffixes), 14-lead dual-in-line plastic packages (E suffix), 14-lead ceramic flat packages (K suffix), and in chip form (H suffix).

The TI-CD4011A, CD4012A, and CD4023A NAND gates provide the system designer with direct implementation of the NAND function and supplement the existing family of CMOS gates

These types are supplied in 14-lead hermetic dual-in-line ceramic packages (D and F suffixes), 14-lead dual-in-line plastic packages (E suffix), 14-lead ceramic flat packages (K suffix), and in chip form (H suffix).
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* Data sheet CMOS NAND Gates datasheet Nov 15, 2001

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