Top

Product details

Parameters

Technology Family CD4000 VCC (Min) (V) 3 VCC (Max) (V) 18 Bits (#) 4 Voltage (Nom) (V) 10 F @ nom voltage (Max) (MHz) 8 ICC @ nom voltage (Max) (mA) 0.03 tpd @ nom Voltage (Max) (ns) 240 IOL (Max) (mA) 1.5 IOH (Max) (mA) -1.5 Function Counter Product type Binary Rating Catalog Operating temperature range (C) -55 to 125 open-in-new Find other Counter, arithmetic & parity function ICs

Package | Pins | Size

PDIP (N) 16 181 mm² 19.3 x 9.4 SOP (NS) 16 80 mm² 10.2 x 7.8 TSSOP (PW) 16 22 mm² 4.4 x 5 open-in-new Find other Counter, arithmetic & parity function ICs

Features

  • Individual clock lines for counting up or counting down
  • Synchronous high-speed carry and borrow propagation delays for cascading
  • Asynchronous reset and preset capability
  • Medium-speed operation–fCL = 8MHz (typ.) @ 10 V
  • 5-V, 10-V, and 15-V parametric ratings
  • Standardized, symmetrical output characteristics
  • 100% tested for quiescent current at 20 V
  • Maximum input current of 1 µA at 18 V over full package-temperature range; 100 nA at 18 V and 25°C
  • Noise margin (full package-temperature range) =
            1 V at VDD = 5 V
            2 V at VDD = 10 V
         2.5 V at VDD = 15 V
  • Meets all requirements of JEDEC Tentative Standard No. 13B, "Standard Specifications for Description of ’B’ Series CMOS Devices"
  • Applications:
    • Up/down difference counting
    • Multistage ripple counting
    • Synchronous frequency dividers
    • A/D and D/A conversion
    • Programmable binary or BCD counting

open-in-new Find other Counter, arithmetic & parity function ICs

Description

CD40192b Presettable BCD Up/Down Counter and the CD40193B Presettable Binary Up/Down Counter each consist of 4 synchronously clocked, gated "D" type flip-flops connected as a counter. The inputs consist of 4 individual jam lines, a PRESET\ ENABLE\ control, individual CLOCK UP and CLOCK DOWN signals and a master RESET. Four buffered Q signal outputs as well as CARRY\ and BORROW\ outputs for multiple-stage counting schemes are provided.

The counter is cleared so that all outputs are in a low state by a high on the RESET line. A RESET is accomplished asynchronously with the clock. Each output is individually programmable asynchronously with the clock to the level on the corresponding jam input when the PRESET\ ENABLE\ control is low.

The counter counts up one count on the positive clock edge of the CLOCK UP signal provided the CLOCK DOWN line is high. The counter counts down on count on the positive clock edge of the CLOCK DOWN signal provided the CLOCK UP line is high.

The CARRY\ and BORROW\ signals are high with the counter is counting up or down. The CARRY\ signal goes low one-half clock cycle after the counter reaches its maximum count in the count-up mode. The BORROW\ signal goes low one-half clock cycle after the counter reaches its minimum count in the count-down mode. Cascading of multiple packages is easily accomplished with out the need for additional external circuitry by tying the BORROW\ and CARRY\ outputs to the CLOCK DOWN and CLOCK UP inputs, respectively, of the succeeding counter package.

The CD40192B and CD40193B types are supplied in 16-lead hermetic dual-in-line ceramic packages (F3A suffix), 16-lead dual-in-line plastic packages (E suffix), 16-lead small-outline packages (NSR suffix), and 16-lead thin shrink small-outline packages (PW and PWR suffixes).

open-in-new Find other Counter, arithmetic & parity function ICs
Download

Technical documentation

= Featured
No results found. Please clear your search and try again. View all 8
Type Title Date
* Datasheet CD40192B, CD40193B TYPES datasheet (Rev. B) Jun. 27, 2003
Selection guides Logic Guide (Rev. AB) Jun. 12, 2017
Application notes Understanding and Interpreting Standard-Logic Data Sheets (Rev. C) Dec. 02, 2015
User guides LOGIC Pocket Data Book (Rev. B) Jan. 16, 2007
Application notes Semiconductor Packing Material Electrostatic Discharge (ESD) Protection Jul. 08, 2004
User guides Signal Switch Data Book (Rev. A) Nov. 14, 2003
More literature Logic Cross-Reference (Rev. A) Oct. 07, 2003
Application notes Understanding Buffered and Unbuffered CD4xxxB Series Device Characteristics Dec. 03, 2001

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Hardware development

EVALUATION BOARDS Download
document-generic User guide
$10.00
Description
This EVM is designed to support any logic device that has a D, DW, DB, NS, PW, P, N, or DGV package in a 14 to 24 pin count.
Features
  • Board design allows for versatility in evaluation
  • Supports a wide-range of logic devices

CAD/CAE symbols

Package Pins Download
PDIP (N) 16 View options
SO (NS) 16 View options
TSSOP (PW) 16 View options

Ordering & quality

Support & training

TI E2E™ forums with technical support from TI engineers

Content is provided "as is" by TI and community contributors and does not constitute TI specifications. See terms of use.

If you have questions about quality, packaging or ordering TI products, see TI support. ​​​​​​​​​​​​​​

Videos

Related videos