CD4041UB

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CMOS quad true/complement buffer

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Product details

Parameters

Technology Family CD4000 VCC (Min) (V) 3 VCC (Max) (V) 18 Channels (#) 4 Inputs per channel 2 IOL (Max) (mA) 24 Input type Standard CMOS IOH (Max) (mA) -24 Output type Push-Pull Features Standard Speed (tpd > 50ns) Data rate (Max) (Mbps) 16 Rating Catalog Operating temperature range (C) -55 to 125 open-in-new Find other Combination gate

Package | Pins | Size

PDIP (N) 14 181 mm² 19.3 x 9.4 SOIC (D) 14 52 mm² 8.65 x 6 TSSOP (PW) 14 32 mm² 5 x 6.4 open-in-new Find other Combination gate

Features

  • Balanced sink and source current; approximately 4 times standard "B" drive
  • Equalized delay to true and complement outputs
  • 100% tested for quiescent current at 20 V
  • Maximum input current of 1 µA at 18 V over full package temperature range; 100nA at 18 V and 25°C
  • 5-V, 10-V, and 15-V parametric ratings
  • Meets all requirements of JEDEC Tentative Standard No. 13A, "Standard Specifications for Description of ’B’ Series CMOS Devices"
  • Applications:
    • High current source/sink driver
    • CMOS-to-DTL/TTL Converter Buffer
    • Display driver
    • MOS clock driver
    • Resistor network driver (Ladder or weighted R)
    • Buffer
    • Transmission line driver

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Description

CD4041UB types are quad true/complement buffers consisting of n- and p-channel units having low channel resistance and high current (sourcing and sinking) capability. The CD4041UB is intended for use as a buffer, line-driver, or CMOS-to-TTL driver. It can be used as an ultra-low power resistor-network driver for A/D and D/A conversion, as a transmission-line driver, and in other applications where high noise immunity and low power dissipation are primary design requirements.

The CD4041UB types are supplied in 14-lead hermetic dual-in-line ceramic packages (F3A suffix), 14-lead dual-in-line plastic packages (E suffix), 14-lead small-outline packages (M, MT, M96, and NSR suffixes), and 14-lead thin shrink small-outline packages (PW and PWR suffixes).

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Technical documentation

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Type Title Date
* Datasheet CD4041UB TYPES datasheet (Rev. C) Aug. 21, 2003
Technical articles How to keep your motor running safely Jun. 04, 2020
Selection guides Logic Guide (Rev. AB) Jun. 12, 2017
Application notes Understanding and Interpreting Standard-Logic Data Sheets (Rev. C) Dec. 02, 2015
User guides LOGIC Pocket Data Book (Rev. B) Jan. 16, 2007
Application notes Semiconductor Packing Material Electrostatic Discharge (ESD) Protection Jul. 08, 2004
User guides Signal Switch Data Book (Rev. A) Nov. 14, 2003
More literature Logic Cross-Reference (Rev. A) Oct. 07, 2003
Application notes Understanding Buffered and Unbuffered CD4xxxB Series Device Characteristics Dec. 03, 2001

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Hardware development

EVALUATION BOARDS Download
document-generic User guide
$10.00
Description
This EVM is designed to support any logic device that has a D, DW, DB, NS, PW, P, N, or DGV package in a 14 to 24 pin count.
Features
  • Board design allows for versatility in evaluation
  • Supports a wide-range of logic devices

CAD/CAE symbols

Package Pins Download
PDIP (N) 14 View options
SOIC (D) 14 View options
TSSOP (PW) 14 View options

Ordering & quality

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