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Parameters

Technology Family CD4000 VCC (Min) (V) 3 VCC (Max) (V) 18 Input type CMOS Output type CMOS IOL (Max) (mA) 4 IOH (Max) (mA) -4 open-in-new Find other Phase-locked-loop (PLL)/oscillator

Package | Pins | Size

PDIP (N) 16 181 mm² 19.3 x 9.4 SOP (NS) 16 80 mm² 10.2 x 7.8 TSSOP (PW) 16 22 mm² 4.4 x 5 open-in-new Find other Phase-locked-loop (PLL)/oscillator

Features

  • Very low power consumption:
       70 µW (typ.) at VCO fo = 10 kHz, VDD = 5 V
  • Operating frequency range up to 1.4 MHz (typ.) at VDD = 10 V, RI = 5 k
  • Low frequency drift: 0.04%/°C (typ.) at VDD = 10 V
  • Choice of two phase comparators:
    • Exclusive-OR network (I)
    • Edge-controlled memory network with phase-pulse output for lock indication (II)
  • High VCO linearity: <1% (typ.) at VDD = 10 V
  • VCO inhibit control for ON-OFF keying and ultra-low standby power consumption
  • Source-follower output of VCO control input (Demod. output)
  • Zener diode to assist supply regulation
  • Standardized, symmetrical output characteristics
  • 100% tested for quiescent current at 20 V
  • 5-V, 10-V, and 15-V parametric ratings
  • Meets all requirements of JEDEC Tentative Standard No. 13B, "Standard Specifications for Description of 'B' Series CMOS Devices"
  • Applications
    • FM demodulator and modulator
    • Frequency synthesis and multiplication
    • Frequency discriminator
    • Data synchronization
    • Voltage-to-frequency conversion
    • Tone decoding
    • FSK - Modems
    • Signal conditioning
    • (See ICAN-6101) "RCA COS/MOS Phase-Locked Loop - A Versatile Building Block for Micropower Digital and Analog Applications"
open-in-new Find other Phase-locked-loop (PLL)/oscillator

Description

CD4046B CMOS Micropower Phase-Locked Loop (PLL) consists of a low-power, linear voltage-controlled oscillator (VCO) and two different phase comparators having a common signal-input amplifier and a common comparator input. A 5.2-V zener diode is provided for supply regulation if necessary.

The CD4046B types are supplied in 16-lead hermetic dual-in-line ceramic packages (F3A suffix), 16-lead dual-in-line plastic packages (E suffix), 16-lead small-outline packages (NSR suffix), and 16-lead thin shrink small-outline packages (PW and PWR suffixes).

open-in-new Find other Phase-locked-loop (PLL)/oscillator
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Technical documentation

= Top documentation for this product selected by TI
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Type Title Date
* Datasheet CD4046B TYPES datasheet (Rev. B) Jun. 27, 2003
Selection guide Logic Guide (Rev. AB) Jun. 12, 2017
Application note Understanding and Interpreting Standard-Logic Data Sheets (Rev. C) Dec. 02, 2015
Technical articles Failure to lock: Why wideband PLL frequency synthesizers lose lock Mar. 22, 2013
User guide LOGIC Pocket Data Book (Rev. B) Jan. 16, 2007
Application note Semiconductor Packing Material Electrostatic Discharge (ESD) Protection Jul. 08, 2004
User guide Signal Switch Data Book (Rev. A) Nov. 14, 2003
More literature Logic Cross-Reference (Rev. A) Oct. 07, 2003
Application note CD4046B Phase-Locked Loop (Rev. A) Feb. 01, 2002
Application note Understanding Buffered and Unbuffered CD4xxxB Series Device Characteristics Dec. 03, 2001

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Hardware development

EVALUATION BOARD Download
10
Description
This EVM is designed to support any logic device that has a D, DW, DB, NS, PW, P, N, or DGV package in a 14 to 24 pin count.
Features
  • Board design allows for versatility in evaluation
  • Supports a wide-range of logic devices

CAD/CAE symbols

Package Pins Download
PDIP (N) 16 View options
SO (NS) 16 View options
TSSOP (PW) 16 View options

Ordering & quality

Information included:
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  • REACH
  • Device marking
  • Lead finish/Ball material
  • MSL rating/Peak reflow
  • MTBF/FIT estimates
  • Material content
  • Qualification summary
  • Ongoing reliability monitoring

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