Packaging information
| Package | Pins TSSOP (PW) | 14 |
| Operating temperature range (°C) -55 to 125 |
| Package qty | Carrier 2,000 | LARGE T&R |
Features for the CD4078B
- Medium-Speed Operation:
tPHL, tPLH = 75 ns (typ.) at VDD = 10 V - Buffered inputs and output
- 5-V, 10-V, and 15-V parametric ratings
- Standardized symmetrical output characteristics
- 100% tested for quiescent current at 20 V
- Maximum input current of 1 µA at 28 V over full package-temperature range:
100 nA at 18 V and 25°C - Noise margin (over full package-temperature range):
- 1 V at VDD = 5 V
- 2 V at VDD = 10 V
- 2.5 V at VDD = 15 V
- Meets all requirements of JEDEC Tentative Standard No. 13B, "Standard Specifications for Description of 'B' Series CMOS Devices"
Description for the CD4078B
CD4078B NOR/OR Gate provides the system designer with direct implementation of the positive-logic 8-input NOR and OR functions and supplements the existing family of CMOS gates.
The CD4078B types are supplied in 14-lead hermetic dual-in-line ceramic packages (F3A suffix), 14-lead dual-in-line plastic packages (E suffix), 14-lead small-outline packages (M, MT, M96, and NSR suffixes), and 14-lead thin shink small-outline packages (PW and PWR suffixes).