CD4085B CMOS Dual 2-Wide 2-Input AND-OR-INVERT Gate | TI.com

CD4085B
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CMOS Dual 2-Wide 2-Input AND-OR-INVERT Gate

CMOS Dual 2-Wide 2-Input AND-OR-INVERT Gate - CD4085B
Datasheet
 

Description

CD4085 contains a pair of AND-OR-INVERT gates, each consisting of two 2-input AND gates driving a 3-input NOR gate. Individual inhibit controls are provided for both A-O-I gates.

The CD4085B types are supplied in 14-lead hermetic dual-in-line ceramic packages (F3A suffix), 14-lead dual-in-line plastic packages (E suffix), 14-lead small-outline packages (M, MT, M96, and NSR suffixes), and 14-lead thin shrink small-outline packages (PW and PWR suffixes).

Features

  • Medium-speed operation - tPHL = 90 ns; tPLH = 125 ns (typ.) at 10 V
  • Individual inhibit controls
  • Standardized symmetrical output characteristics
  • 100% tested for quiescent current at 20 V
  • Maximum input current of 1 µA at 18 V over full package-temperature range; 100 nA at 18 V and 25°C
  • Noise margin (over full package-temperature range):
    • 1 V at VDD = 5 V
    • 2 V at VDD = 10 V
    • 2.5 V at VDD = 15 V
  • 5-V, 10-V, and 15-V parametric ratings
  • Meets all requirements of JEDEC Tentative Standard No. 13B, "Standard Specifications for Description of 'B' Series CMOS Devices"

Parametrics

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Part number Order Technology Family VCC (Min) (V) VCC (Max) (V) Channels (#) Inputs per channel IOL (Max) (mA) Input type IOH (Max) (mA) Output type Features Data rate (Max) (Mbps) Rating Operating temperature range (C) Package size: mm2:W x L (PKG) Package Group
CD4085B Order now CD4000     3     18     2     2     6.8     Standard CMOS     -6.8     Push-Pull     Standard Speed (tpd > 50ns)     8     Catalog     -55 to 125     14PDIP: 181 mm2: 9.4 x 19.3 (PDIP | 14)
14SOIC: 52 mm2: 6 x 8.65 (SOIC | 14)
14TSSOP: 32 mm2: 6.4 x 5 (TSSOP | 14)    
PDIP | 14
SOIC | 14
TSSOP | 14