CD4572UB CMOS Hex Gate (with 4 Inverters, One 2-Input NOR Gate, and One 2-Input NAND Gate) | TI.com

CD4572UB
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CMOS Hex Gate (with 4 Inverters, One 2-Input NOR Gate, and One 2-Input NAND Gate)

CMOS Hex Gate (with 4 Inverters, One 2-Input NOR Gate, and One 2-Input NAND Gate) - CD4572UB
Datasheet
 

Description

CD4572UB Hex Gate provides the system designer with direct implementation of inverter, NAND, and NOR functions and supplements the existing family of CMOS gates.

The CD4572UB devices meet all requirements of JEDEC Standard No. 13B, "Standard Specifications for Description of 'B' Series CMOS Devices."

The CD4572UB types are supplied in 16-lead dual-in-line plastic packages (E suffix), 16-lead small-outline packages (M, M96, MT, and NSR suffixes), and 16-lead thin shrink small-outline packages (PW and PWR suffixes).

Features

  • Pin 7 NOR input positioned adjacent to VSS for easy use of gate as an inverter
  • Pin 15 NAND input positioned adjacent to VDD for easy use of gate as an inverter
  • Standard symmetrical output characteristics
  • 100% tested for quiescent current at 20 V
  • Maximum input current of 1 µA at 18 V over full package-temperature range:
       100 nA at 18 V and 25°C
  • 5-V, 10-V, and 15-V parametric ratings
  • Meets all requirements of JEDEC Tentative Standard No. 13B, "Standard Specifications for Description of 'B' Series CMOS Devices"

Parametrics

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Part number Order Technology Family VCC (Min) (V) VCC (Max) (V) Channels (#) Inputs per channel IOL (Max) (mA) IOH (Max) (mA) Features Data rate (Max) (Mbps) Rating Operating temperature range (C) Package size: mm2:W x L (PKG) Package Group
CD4572UB Order now CD4000     3     18     6     2     6.8     -6.8     Standard Speed (tpd > 50ns)     16     Catalog     -55 to 125     16PDIP: 181 mm2: 9.4 x 19.3 (PDIP | 16)
16SO: 80 mm2: 7.8 x 10.2 (SO | 16)
16SOIC: 59 mm2: 6 x 9.9 (SOIC | 16)
16TSSOP: 22 mm2: 4.4 x 5 (TSSOP | 16)    
PDIP | 16
SOIC | 16
SO | 16
TSSOP | 16