CD54HC112

ACTIVE

High Speed CMOS Logic Dual J-K Flip-Flops with Set and Reset, Negative-Edge Trigger

Product details

Number of channels 2 Technology family HC Input type LVTTL/CMOS Output type Push-Pull Clock frequency (MHz) 20 Supply current (max) (µA) 80 IOL (max) (mA) -6 IOH (max) (mA) 6 Features Balanced outputs, Clear, High speed (tpd 10-50ns), Negative edge triggered, Positive input clamp diode, Preset Operating temperature range (°C) -55 to 125 Rating Military
Number of channels 2 Technology family HC Input type LVTTL/CMOS Output type Push-Pull Clock frequency (MHz) 20 Supply current (max) (µA) 80 IOL (max) (mA) -6 IOH (max) (mA) 6 Features Balanced outputs, Clear, High speed (tpd 10-50ns), Negative edge triggered, Positive input clamp diode, Preset Operating temperature range (°C) -55 to 125 Rating Military
CDIP (J) 16 135.3552 mm² (— mm × — mm)
There are no details available for this product.
Download

Technical documentation

No results found. Please clear your search and try again.
View all 1
Top documentation Type Title Format options Date
* Data sheet CDx4HC112, CDx4HCT112 Dual J-K Flip-Flop with Set and Reset with Negative-Edge Trigger datasheet (Rev. J) PDF | HTML Oct 14, 2022

Ordering & quality

Support & training

TI E2E™ forums with technical support from TI engineers

Content is provided "as is" by TI and community contributors and does not constitute TI specifications. See terms of use.

If you have questions about quality, packaging or ordering TI products, see TI support. ​​​​​​​​​​​​​​