Home Logic & voltage translation Flip-flops, latches & registers JK flip-flops
Home
Logic & voltage translation
Flip-flops, latches & registers
JK flip-flops

CD54HC73

ACTIVE

High Speed CMOS Logic Dual Negative-Edge Trigger J-K Flip-Flops with Reset

Order now
Data sheet

CD54HC73

ACTIVE
Data sheet Order now

Product details

Number of channels 2 Technology family HC Input type LVTTL/CMOS IOL (max) (mA) -6 IOH (max) (mA) 6 Operating temperature range (°C) -55 to 125 Rating Military
Number of channels 2 Technology family HC Input type LVTTL/CMOS IOL (max) (mA) -6 IOH (max) (mA) 6 Operating temperature range (°C) -55 to 125 Rating Military
CDIP (J) 14 130.4652 mm² (— mm × — mm)
  • Hysteresis on clock inputs for improved noise immunity and increased input rise and fall times
  • Asynchronous reset
  • Complementary outputs
  • Buffered inputs
  • Typical fMAX = 60 MHz at VCC = 5 V, CL = 15 pF, TA = 25℃
  • Fanout (over temperature range)
    • Standard outputs: 10 LSTTL loads
    • Bus driver outputs: 15 LSTTL loads
  • Wide operating temperature range: –55℃ to 125℃
  • Balanced propagation delay and transition times
  • Significant power reduction compared to LSTTL Logic ICs
  • HC types
    • 2 V to 6V operation
    • High noise immunity: NIL = 30%, NIH = 30% of VCC at VCC = 5 V
  • HCT types
    • 4.5 V to 5.5 V operation
    • Direct LSTTL input logic compatibility, VIL = 0.8 V (max), VIH = 2 V (min)
    • CMOS input compatibility, II ≤ 1 µA at VOL, VOH
  • Hysteresis on clock inputs for improved noise immunity and increased input rise and fall times
  • Asynchronous reset
  • Complementary outputs
  • Buffered inputs
  • Typical fMAX = 60 MHz at VCC = 5 V, CL = 15 pF, TA = 25℃
  • Fanout (over temperature range)
    • Standard outputs: 10 LSTTL loads
    • Bus driver outputs: 15 LSTTL loads
  • Wide operating temperature range: –55℃ to 125℃
  • Balanced propagation delay and transition times
  • Significant power reduction compared to LSTTL Logic ICs
  • HC types
    • 2 V to 6V operation
    • High noise immunity: NIL = 30%, NIH = 30% of VCC at VCC = 5 V
  • HCT types
    • 4.5 V to 5.5 V operation
    • Direct LSTTL input logic compatibility, VIL = 0.8 V (max), VIH = 2 V (min)
    • CMOS input compatibility, II ≤ 1 µA at VOL, VOH
filter Find other JK flip-flops
There are no details available for this product.
open-in-new Find other JK flip-flops
Download

Technical documentation

No results found. Please clear your search and try again.
View all 2
Top documentation Type Title Format options Date
* Data sheet CDx4HC73 CD74HCT73 Dual J-K Flip-Flop with Reset Negative-Edge Trigger datasheet (Rev. G) PDF | HTML Oct 12, 2022
* SMD CD54HC73 SMD 5962-85153 Jun 21, 2016

Ordering & quality

Support & training

TI E2E™ forums with technical support from TI engineers

View all forum topics

Content is provided "as is" by TI and community contributors and does not constitute TI specifications. See terms of use.

If you have questions about quality, packaging or ordering TI products, see TI support. ​​​​​​​​​​​​​​