CD74HC21 High Speed CMOS Logic Dual 4-Input AND Gates | TI.com

CD74HC21
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High Speed CMOS Logic Dual 4-Input AND Gates

High Speed CMOS Logic Dual 4-Input AND Gates - CD74HC21
Datasheet
 

Description

The ’HC21 and CD74HCT21 logic gates utilize silicon gate CMOS technology to achieve operating speeds similar to LSTTL gates with the low power consumption of standard CMOS integrated circuits. All devices have the ability to drive 10 LSTTL loads. The HCT logic family is functionally pin compatible with the standard LS logic family.

Features

  • Buffered Inputs
  • Typical Propagation Delay: 9ns at VCC = 5V, CL = 15pF, TA = 25°C
  • Fanout (Over Temperature Range)
    • Standard Outputs . . . . . . . . 10 LSTTL Loads
    • Bus Driver Outputs . . . . . . 15 LSTTL Loads
  • Wide Operating Temperature Range . . . -55°C to 125°C
  • Balanced Propagation Delay and Transition Times
  • Significant Power Reduction Compared to LSTTL Logic ICs
  • HC Types
    • 2V to 6V Operation
    • High Noise Immunity: NIL = 30%, NIH = 30% of VCC at VCC = 5V
  • HCT Types
    • 4.5V to 5.5V Operation
    • Direct LSTTL Input Logic Compatibility, VIL = 0.8V (Max), VIH = 2V (Min)
    • CMOS Input Compatibility, Il 1µA at VOL, VOH

Data sheet acquired from Harris Semiconductor

Parametrics

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Part number Order Technology Family VCC (Min) (V) VCC (Max) (V) Channels (#) Inputs per channel IOL (Max) (mA) IOH (Max) (mA) Input type Output type Features Data rate (Max) (Mbps) Rating Operating temperature range (C) Package size: mm2:W x L (PKG) Package Group
CD74HC21 Order now HC     2     6     2     4     5.2     -5.2     Standard CMOS     Push-Pull     High Speed (tpd 10-50ns)     28     Catalog     -55 to 125     14PDIP: 181 mm2: 9.4 x 19.3 (PDIP | 14)
14SOIC: 52 mm2: 6 x 8.65 (SOIC | 14)    
PDIP | 14
SOIC | 14    
CD54HC21 Samples not available HC     2     6     2     4     5.2     -5.2     Standard CMOS     Push-Pull     High Speed (tpd 10-50ns)     28     Military     -55 to 125     14CDIP: 130 mm2: 6.67 x 19.56 (CDIP | 14)     CDIP | 14