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CD74HCT10

NOT RECOMMENDED FOR NEW DESIGNS
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Data sheet
CD74HCT10 is not recommended for new designs
This product continues to be available for existing customers. New designs should consider an alternate product.
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Similar functionality to the compared device.
SN74ACT10 ACTIVE 3-ch, 3-input, 1.5V to 6V 24mA drive strength NAND gate with TTL compatible inputs Voltage range 4.5V to 5.5V, average propagation delay 8ns, average drive strength 24mA

CD74HCT10

NOT RECOMMENDED FOR NEW DESIGNS
Data sheet Order now

Product details

Technology family HCT Number of channels 3 Inputs per channel 3 IOL (max) (mA) 4 IOH (max) (mA) -4 Input type TTL-Compatible CMOS Output type Push-Pull Features High speed (tpd 10-50ns) Data rate (max) (Mbps) 25 Rating Catalog Operating temperature range (°C) -55 to 125
Technology family HCT Number of channels 3 Inputs per channel 3 IOL (max) (mA) 4 IOH (max) (mA) -4 Input type TTL-Compatible CMOS Output type Push-Pull Features High speed (tpd 10-50ns) Data rate (max) (Mbps) 25 Rating Catalog Operating temperature range (°C) -55 to 125
PDIP (N) 14 181.42 mm² (19.3 mm × 9.4 mm) SOIC (D) 14 51.9 mm² (8.65 mm × 6 mm)
  • LSTTL input logic compatible
    • VIL(max) = 0.8 V, VIH(min) = 2 V
  • CMOS input logic compatible
    • II ≤ 1 µA at VOL, VOH
  • Buffered inputs
  • 4.5 V to 5.5 V operation
  • Wide operating temperature range: -55°C to +125°C
  • Supports fanout up to 10 LSTTL loads
  • Significant power reduction compared to LSTTL logic ICs
  • LSTTL input logic compatible
    • VIL(max) = 0.8 V, VIH(min) = 2 V
  • CMOS input logic compatible
    • II ≤ 1 µA at VOL, VOH
  • Buffered inputs
  • 4.5 V to 5.5 V operation
  • Wide operating temperature range: -55°C to +125°C
  • Supports fanout up to 10 LSTTL loads
  • Significant power reduction compared to LSTTL logic ICs

This device contains three independent 3-input NAND gates. Each gate performs the Boolean function Y =  A ● B ● C in positive logic.

This device contains three independent 3-input NAND gates. Each gate performs the Boolean function Y =  A ● B ● C in positive logic.
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* Data sheet CD54HCT10, CD74HCT10 High-Speed CMOS Logic Triple 3-Input NAND Gate datasheet Aug 30, 2019

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