Product details

Technology Family HCT Function Digital Multiplexer Configuration 2:1 Number of channels (#) 4 Operating temperature range (C) -55 to 125 Rating Catalog
Technology Family HCT Function Digital Multiplexer Configuration 2:1 Number of channels (#) 4 Operating temperature range (C) -55 to 125 Rating Catalog
PDIP (N) 16 181 mm² 19.3 x 9.4
  • 4.5-V to 5.5-V VCC Operation
  • Wide Operating Temperature Range of –55°C to 125°C
  • Balanced Propagation Delays and Transition Times
  • Standard Outputs Drive Up To 10 LS-TTL Loads
  • Significant Power Reduction Compared to LS-TTL Logic ICs
  • Inputs Are TTL-Voltage Compatible
  • 4.5-V to 5.5-V VCC Operation
  • Wide Operating Temperature Range of –55°C to 125°C
  • Balanced Propagation Delays and Transition Times
  • Standard Outputs Drive Up To 10 LS-TTL Loads
  • Significant Power Reduction Compared to LS-TTL Logic ICs
  • Inputs Are TTL-Voltage Compatible

These devices are designed to multiplex signals from 4-bit data sources to 4-output data lines in bus-organized systems. The 3-state outputs do not load the data lines when the output-enable (G)\ input is at a high logic level.

To ensure the high-impedance state during power up or power down, G\ should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

These devices are designed to multiplex signals from 4-bit data sources to 4-output data lines in bus-organized systems. The 3-state outputs do not load the data lines when the output-enable (G)\ input is at a high logic level.

To ensure the high-impedance state during power up or power down, G\ should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

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Technical documentation

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Type Title Date
* Data sheet CD54HCT258, CD74HCT258 datasheet (Rev. A) 18 Apr 2003
Application note Implications of Slow or Floating CMOS Inputs (Rev. E) 26 Jul 2021
Selection guide Logic Guide (Rev. AB) 12 Jun 2017
Application note Understanding and Interpreting Standard-Logic Data Sheets (Rev. C) 02 Dec 2015
User guide LOGIC Pocket Data Book (Rev. B) 16 Jan 2007
Application note Semiconductor Packing Material Electrostatic Discharge (ESD) Protection 08 Jul 2004
User guide Signal Switch Data Book (Rev. A) 14 Nov 2003
More literature Logic Cross-Reference (Rev. A) 07 Oct 2003
Application note TI IBIS File Creation, Validation, and Distribution Processes 29 Aug 2002
Application note CMOS Power Consumption and CPD Calculation (Rev. B) 01 Jun 1997
Application note Designing With Logic (Rev. C) 01 Jun 1997
Application note SN54/74HCT CMOS Logic Family Applications and Restrictions 01 May 1996
Application note Using High Speed CMOS and Advanced CMOS in Systems With Multiple Vcc 01 Apr 1996

Design & development

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Evaluation board

14-24-LOGIC-EVM — Generic Logic EVM Supporting 14 through 24 Pin PW, DB, D, DW, NS, DYY, and DGV Packages

This EVM is designed to support any logic device that has a D, DW, DB, NS, PW, DYY or DGV package in a 14 to 24 pin count.

User guide: PDF | HTML
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PDIP (N) 16 View options

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