The \x92FCT646T devices consist of a bus transceiver circuit with 3-state, D-type flip-flops, and control circuitry arranged for multiplexed transmission of data directly from the input bus or from the internal registers. Data on the A or B bus is clocked into the registers as the appropriate clock pin goes to a high logic level. Output-enable (G\) and direction (DIR) inputs control the transceiver function. In the transceiver mode,data present at the high-impedance port can be stored in either the A or B register, or in both. Select controls (SAB, SBA) can multiplex stored and real-time (transparent mode) data. DIR determines which bus receives data when G\ is low. In the isolation mode (G\ is high), A data can be stored in the B register and/or B data can be stored in the A register.
These devices are fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.
| Top documentation | Type | Title | Format options | Date |
|---|---|---|---|---|
| * | Data sheet | 8-Bit Registered Transceivers With 3-State Outputs datasheet (Rev. A) | Oct 1, 2001 | |
| * | User guide | CYFCT Parameter Measurement Information | Apr 2, 2001 | |
| * | SMD | CY54FCT646T SMD 5962-92223 | Jun 21, 2016 |
For additional terms or required resources, click any title below to view the detail page where available.
| Package | Pins | CAD symbols, footprints & 3D models |
|---|---|---|
| LCCC (FK) | 28 | Ultra Librarian |
| CDIP (JT) | 24 | Ultra Librarian |
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