CY74FCT827T

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10-ch, 4.75-V to 5.25-V buffers with TTL-compatible CMOS inputs and 3-state outputs

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Product details

Parameters

Technology Family FCT Supply voltage (Min) (V) 4.75 Supply voltage (Max) (V) 5.25 Number of channels (#) 10 IOL (Max) (mA) 64 ICC (Max) (uA) 500 IOH (Max) (mA) -32 Input type TTL-Compatible CMOS Output type 3-State Features Very high speed (tpd 5-10ns), Over-voltage tolerant inputs Rating Catalog open-in-new Find other Non-Inverting buffer/driver

Package | Pins | Size

SOIC (DW) 24 160 mm² 15.5 x 10.3 SSOP (DBQ) 24 52 mm² 8.65 x 6 open-in-new Find other Non-Inverting buffer/driver

Features

  • Function, Pinout, and Drive Compatible With FCT, F, and AM29827 Logic
  • Reduced VOH (Typically = 3.3 V) Versions of Equivalent FCT Functions
  • Edge-Rate Control Circuitry for Significantly Improved Noise Characteristics
  • Ioff Supports Partial-Power-Down Mode Operation
  • ESD Protection Exceeds JESD 22
    • 2000-V Human-Body Model (A114-A)
    • 200-V Machine Model (A115-A)
    • 1000-V Charged-Device Model (C101)
  • 3-State Outputs
  • Matched Rise and Fall Times
  • Fully Compatible With TTL Input and Output Logic Levels
  • CY54FCT827T
    • 32-mA Output Sink Current
    • 12-mA Output Source Current
  • CY74FCT827T
    • 64-mA Output Sink Current
    • 32-mA Output Source Current

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Description

The \x92FCT827T devices are 10-bit bus drivers that provide high-performance bus-interface buffering for wide data/address paths or buses carrying parity. The 10-bit buffers have NANDed output enables for maximum control flexibility. The \x92FCT827T devices are designed for high-capacitance-load drive capability, while providing low-capacitance bus loading at both inputs and outputs. All outputs are designed for low-capacitance bus loading in the high-impedance state.

This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.

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Technical documentation

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Type Title Date
* Data sheet 10-Bit Buffers With 3-State Outputs datasheet (Rev. A) Oct. 01, 2001
Selection guide Logic Guide (Rev. AB) Jun. 12, 2017
Application note Understanding and Interpreting Standard-Logic Data Sheets (Rev. C) Dec. 02, 2015
User guide LOGIC Pocket Data Book (Rev. B) Jan. 16, 2007
Application note Semiconductor Packing Material Electrostatic Discharge (ESD) Protection Jul. 08, 2004
Application note Selecting the Right Level Translation Solution (Rev. A) Jun. 22, 2004
More literature Logic Cross-Reference (Rev. A) Oct. 07, 2003
User guide CYFCT Parameter Measurement Information Apr. 02, 2001
Selection guide Advanced Bus Interface Logic Selection Guide Jan. 09, 2001

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Hardware development

EVALUATION BOARD Download
document-generic User guide
10
Description
This EVM is designed to support any logic device that has a D, DW, DB, NS, PW, P, N, or DGV package in a 14 to 24 pin count.
Features
  • Board design allows for versatility in evaluation
  • Supports a wide-range of logic devices

Design tools & simulation

SIMULATION MODEL Download
SCCM016.ZIP (7 KB) - PSpice Model

CAD/CAE symbols

Package Pins Download
SOIC (DW) 24 View options
SSOP (DBQ) 24 View options

Ordering & quality

Information included:
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  • REACH
  • Device marking
  • Lead finish/Ball material
  • MSL rating/Peak reflow
  • MTBF/FIT estimates
  • Material content
  • Qualification summary
  • Ongoing reliability monitoring

Support & training

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