Packaging information
| Package | Pins HTQFP (PHP) | 48 |
| Package qty | Carrier 1,000 | LARGE T&R |
Features for the DAC90802
- INL: 1.9ppm (±0.5LSB at 18 bits)
- DNL: 1.9ppm (±0.5LSB at 18 bits)
- VREF range: ±21V
- Integrated ±21V output buffer with high slew rate
- Digitally controlled gain options: 1 ×, 2 ×, and 4 ×
- 50ns settling to 0.1%FSR with 140pVs glitch
- Reference multiplying bandwidth: 25MHz, MFE −90dB at 100kHz
- THD at ±5V output: −125dB (2kHz) and −110dB (100kHz)
- QSPI™-compatible interface: 33MUPS in 16-bit high-speed mode at 66MHz DDR
- Double-buffered registers with per-channel LDAC pins
- Internal power on reset
- Separate 4Q multiplying, Kelvin-connected reference inputs
- Integrated ground buffer
Description for the DAC90802
The DAC90802 is a dual‐channel 18-bit, multiplying digital-to-analog converter (MDAC) capable of ±23.5V supply span operation. This device supports a dynamic signal range of ±21V for the reference inputs, and voltage feedback at the RFB pin, where gain options of 1 ×, 2 ×, and 4 × are digitally selectable. The output pins, VOUT support the full output range from VREFP to VREFN.
The DAC90802 provides a low-noise voltage output, and true Kelvin-connection accesses to the integrated configuration resistors of the MDAC. This device maintains very-low thermal variation and excellent long-term drift performance in the core R-2R ladder. The DAC90802 implements selectable optimizations for use in arbitrary waveform generation (AWG) mode, fast-settling mode, or multiplying mode.
A 66MHz serial data interface with up to four serial data lines (SDIO0 through SDIO3) in dual data rate (DDR) mode, supports update rates up to 33MUPS in high-speed 16-bit mode, and 22MUPS in high resolution 18-bit mode. The per-channel edge-sensitive load-DAC LDAC inputs allow fine skew control of the DAC. The DAC90802 supports device reset using the RESET pin.