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Product details

Parameters

DDR memory type DDR, DDR2, DDR3, DDR3L Control mode Iout VTT (Max) (A) 1.5 Iq (Typ) (mA) 0.32 Output VREF, VTT Vin (Min) (V) 1.35 Vin (Max) (V) 5.5 Features Shutdown Pin for S3 Rating Catalog Operating temperature range (C) 0 to 125 open-in-new Find other DDR memory power ICs

Package | Pins | Size

HSOIC (DDA) 8 19 mm² 4.9 x 3.9 open-in-new Find other DDR memory power ICs

Features

  • 1.35V Minimum VDDQ
  • Source and Sink Current
  • Low Output Voltage Offset
  • No External Resistors Required
  • Linear Topology
  • Suspend to Ram (STR) Functionality
  • Low External Component Count
  • Thermal Shutdown
  • LP2998/8Q recommended for
    –40°C to 125°C
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Description

The LP2996A linear regulator is designed to meet the JEDEC SSTL-2 specifications for termination of DDR-SDRAM. The device also supports DDR2, DDR3 and DDR3L VTT bus termination with VDDQ min of 1.35V. The device contains a high-speed operational amplifier to provide excellent response to load transients. The output stage prevents shoot through while delivering 1.5A continuous current and transient peaks up to 3A in the application as required for DDR-SDRAM termination. The LP2996A also incorporates a VSENSE pin to provide superior load regulation and a VREF output as a reference for the chipset and DIMMs.

An additional feature found on the LP2996A is an active low shutdown (SD) pin that provides Suspend To RAM (STR) functionality. When SD is pulled low the VTT output will tri-state providing a high impedance output, but, VREF will remain active. A power savings advantage can be obtained in this mode through lower quiescent current.

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Technical documentation

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Type Title Date
* Data sheet LP2996A DDR Termination Regulator datasheet Jun. 27, 2014
Application note Limiting DDR Termination Regulators’ Inrush Current Aug. 23, 2016

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Hardware development

EVALUATION BOARD Download
document-generic User guide
10
Description

The LP2998 evaluation board is designed to provide the design Engineer with a fully functional prototype system in which to evaluate the LP2998 in both a static environment and with a complete memory system.

Design tools & simulation

SIMULATION MODEL Download
SNOM562.ZIP (85 KB) - PSpice Model
SIMULATION MODEL Download
SNOM564.ZIP (7 KB) - PSpice Model

Reference designs

REFERENCE DESIGNS Download
High efficiency power supply architecture reference design for protection relay processor module
TIDA-010011 — This reference design showcases various power architectures for generating multiple voltage rails for an application processor module, requiring >1A load current and high efficiency . The required power supply is generated using 5-, 12- or 24-V DC input from the backplane. Power supplies are (...)
document-generic Schematic
REFERENCE DESIGNS Download
66AK2Gx DSP + ARM Processor Power Solution Reference Design
TIDEP0067 — This reference design is  based on the 66AK2Gx multicore System-on-Chip (SoC) processor and companion TPS65911 power management integrated circuit (PMIC) which includes power supplies and power sequencing for the 66AK2Gx processor in a single device. This power solution design also includes the (...)
document-generic Schematic

CAD/CAE symbols

Package Pins Download
SO PowerPAD (DDA) 8 View options

Ordering & quality

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  • Ongoing reliability monitoring

Recommended products may have parameters, evaluation modules or reference designs related to this TI product.

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