SN54AHC86

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Military 4-ch, 2-input, 2-V to 5.5-V XOR (exclusive OR) gates

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Product details

Parameters

Technology Family AHC Supply voltage (Min) (V) 2 Supply voltage (Max) (V) 5.5 Number of channels (#) 4 Inputs per channel 2 IOL (Max) (mA) 50 Input type Standard CMOS IOH (Max) (mA) -50 Output type Push-Pull Features Over-voltage tolerant inputs, Very high speed (tpd 5-10ns) Data rate (Max) (Mbps) 110 Rating Military Operating temperature range (C) -55 to 125 open-in-new Find other XOR (exclusive OR) gates

Package | Pins | Size

CDIP (J) 14 130 mm² 19.94 x 6.73 CFP (W) 14 55 mm² 9.2 x 6.39 LCCC (FK) 20 79 mm² 8.89 x 8.89 open-in-new Find other XOR (exclusive OR) gates

Features

  • Operating Range 2-V to 5.5-V VCC
  • Latch-Up Performance Exceeds 250 mA Per JESD 17
  • ESD Protection Exceeds JESD 22
    • 2000-V Human-Body Model (A114-A)
    • 200-V Machine Model (A115-A)
    • 1000-V Charged-Device Model (C101)

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Description

The ’AHC86 devices are quadruple 2-input exclusive-OR gates. These devices perform the Boolean function Y = A ⊕ B or Y = AB + AB in positive logic.

A common application is as a true/complement element. If one of the inputs is low, the other input is reproduced in true form at the output. If one of the inputs is high, the signal on the other input is reproduced inverted at the output.

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Technical documentation

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Type Title Date
* Data sheet SN54AHC86, SN74AHC86 datasheet (Rev. J) Jun. 27, 2013
* SMD SN54AHC86 SMD 5962-96816 Jun. 21, 2016
Application note Implications of Slow or Floating CMOS Inputs (Rev. E) Jul. 26, 2021
Selection guide Little Logic Guide 2018 (Rev. G) Jul. 06, 2018
Selection guide Logic Guide (Rev. AB) Jun. 12, 2017
Application note How to Select Little Logic (Rev. A) Jul. 26, 2016
Application note Understanding and Interpreting Standard-Logic Data Sheets (Rev. C) Dec. 02, 2015
User guide LOGIC Pocket Data Book (Rev. B) Jan. 16, 2007
More literature Design Summary for WCSP Little Logic (Rev. B) Nov. 04, 2004
Application note Semiconductor Packing Material Electrostatic Discharge (ESD) Protection Jul. 08, 2004
Application note Selecting the Right Level Translation Solution (Rev. A) Jun. 22, 2004
More literature Logic Cross-Reference (Rev. A) Oct. 07, 2003
Application note Advanced High-Speed CMOS (AHC) Logic Family (Rev. C) Dec. 02, 2002
Application note Texas Instruments Little Logic Application Report Nov. 01, 2002
Application note TI IBIS File Creation, Validation, and Distribution Processes Aug. 29, 2002
Design guide AHC/AHCT Designer's Guide February 2000 (Rev. D) Feb. 24, 2000
Application note Benefits & Issues of Migrating 5-V and 3.3-V Logic to Lower-Voltage Supplies (Rev. A) Sep. 08, 1999
More literature Military Advanced High-Speed CMOS Logic (AHC/AHCT) (Rev. C) Apr. 01, 1998
Application note Migration From 3.3-V To 2.5-V Power Supplies For Logic Devices Dec. 01, 1997
Application note Bus-Interface Devices With Output-Damping Resistors Or Reduced-Drive Outputs (Rev. A) Aug. 01, 1997
Application note CMOS Power Consumption and CPD Calculation (Rev. B) Jun. 01, 1997
Application note Live Insertion Oct. 01, 1996

Design & development

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CAD/CAE symbols

Package Pins Download
CDIP (J) 14 View options
CFP (W) 14 View options
LCCC (FK) 20 View options

Ordering & quality

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