Product details

Number of channels (#) 2 Technology Family ALS Supply voltage (Min) (V) 4.5 Supply voltage (Max) (V) 5.5 Input type Bipolar Output type Push-Pull Clock Frequency (Max) (MHz) 75 IOL (Max) (mA) 8 IOH (Max) (mA) -0.4 ICC (Max) (uA) 4000 Features High speed (tpd 10-50ns)
Number of channels (#) 2 Technology Family ALS Supply voltage (Min) (V) 4.5 Supply voltage (Max) (V) 5.5 Input type Bipolar Output type Push-Pull Clock Frequency (Max) (MHz) 75 IOL (Max) (mA) 8 IOH (Max) (mA) -0.4 ICC (Max) (uA) 4000 Features High speed (tpd 10-50ns)
CDIP (J) 14 130 mm² 19.94 x 6.73 CFP (W) 14 55 mm² 9.2 x 6.39 LCCC (FK) 20 79 mm² 8.89 x 8.89
  • Package Options Include Plastic Small-Outline (D) Packages, Ceramic Chip Carriers (FK), and Standard Plastic (N) and Ceramic (J) 300-mil DIPs
  • Package Options Include Plastic Small-Outline (D) Packages, Ceramic Chip Carriers (FK), and Standard Plastic (N) and Ceramic (J) 300-mil DIPs

These devices contain two independent positive-edge-triggered D-type flip-flops. A low level at the preset () or clear () inputs sets or resets the outputs regardless of the levels of the other inputs. When and are inactive (high), data at the data (D) input meeting the setup-time requirements are transferred to the outputs on the positive-going edge of the clock (CLK) pulse. Clock triggering occurs at a voltage level and is not directly related to the rise time of CLK. Following the hold-time interval, data at the D input can be changed without affecting the levels at the outputs.

The SN54ALS74A and SN54AS74A are characterized for operation over the full military temperature range of -55°C to 125°C. The SN74ALS74A and SN74AS74A are characterized for operation from 0°C to 70°C.

 

These devices contain two independent positive-edge-triggered D-type flip-flops. A low level at the preset () or clear () inputs sets or resets the outputs regardless of the levels of the other inputs. When and are inactive (high), data at the data (D) input meeting the setup-time requirements are transferred to the outputs on the positive-going edge of the clock (CLK) pulse. Clock triggering occurs at a voltage level and is not directly related to the rise time of CLK. Following the hold-time interval, data at the D input can be changed without affecting the levels at the outputs.

The SN54ALS74A and SN54AS74A are characterized for operation over the full military temperature range of -55°C to 125°C. The SN74ALS74A and SN74AS74A are characterized for operation from 0°C to 70°C.

 

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Technical documentation

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Type Title Date
* Data sheet Dual Positive-Edge-Triggered D-Type Flip-Flops With Clear And Preset datasheet (Rev. C) 01 Aug 1995
* SMD SN54ALS74A SMD 84011012A 21 Jun 2016
Selection guide Logic Guide (Rev. AB) 12 Jun 2017
Application note Understanding and Interpreting Standard-Logic Data Sheets (Rev. C) 02 Dec 2015
Application note Power-Up Behavior of Clocked Devices (Rev. A) 06 Feb 2015
User guide LOGIC Pocket Data Book (Rev. B) 16 Jan 2007
Application note Semiconductor Packing Material Electrostatic Discharge (ESD) Protection 08 Jul 2004
More literature Logic Cross-Reference (Rev. A) 07 Oct 2003
Application note TI IBIS File Creation, Validation, and Distribution Processes 29 Aug 2002
Application note Bus-Interface Devices With Output-Damping Resistors Or Reduced-Drive Outputs (Rev. A) 01 Aug 1997
Application note Designing With Logic (Rev. C) 01 Jun 1997
Application note Input and Output Characteristics of Digital Integrated Circuits 01 Oct 1996
Application note Live Insertion 01 Oct 1996
Application note Advanced Schottky (ALS and AS) Logic Families 01 Aug 1995

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CDIP (J) 14 View options
CFP (W) 14 View options
LCCC (FK) 20 View options

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