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SN54HC109-SP

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QML-V, Dual J-K Positive-Edge-Triggered Flip-Flops With Clear And Preset

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Data sheet

SN54HC109-SP

ACTIVE
Data sheet Order now

Product details

Number of channels 2 Technology family HC Input type CMOS Output type Push-Pull Clock frequency (MHz) 20 Supply current (max) (µA) 80 IOL (max) (mA) -4 IOH (max) (mA) 4 Features Balanced outputs, Clear, High speed (tpd 10-50ns), Positive edge triggered, Positive input clamp diode, Preset Operating temperature range (°C) -55 to 125 Rating Space
Number of channels 2 Technology family HC Input type CMOS Output type Push-Pull Clock frequency (MHz) 20 Supply current (max) (µA) 80 IOL (max) (mA) -4 IOH (max) (mA) 4 Features Balanced outputs, Clear, High speed (tpd 10-50ns), Positive edge triggered, Positive input clamp diode, Preset Operating temperature range (°C) -55 to 125 Rating Space
CFP (W) 16 69.319 mm² (— mm × — mm)
  • Wide operating voltage range of 2 V to 6 V
  • Low input current of 1 µA max
  • High-current outputs drive up to 10 LSTTL loads
  • Low power consumption, 40-µA max ICC
  • Typical tpd = 12 ns
  • ±4-mA output drive at 5 V
  • Wide operating voltage range of 2 V to 6 V
  • Low input current of 1 µA max
  • High-current outputs drive up to 10 LSTTL loads
  • Low power consumption, 40-µA max ICC
  • Typical tpd = 12 ns
  • ±4-mA output drive at 5 V
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Top documentation Type Title Format options Date
* Data sheet SNx4HC109 Dual J-K Positive-Edge-Triggered Flip-Flops With Clear and Preset datasheet (Rev. C) PDF | HTML Jun 30, 2022
* SMD SN54HC109-SP SMD 5962-84150 Jul 8, 2016

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