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SN54HC138-SP

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QML-V, 3-Line To 8-Line Decoders/Demultiplexers

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Data sheet

SN54HC138-SP

ACTIVE
Data sheet Order now

Product details

Technology family HC Number of channels 1 Operating temperature range (°C) -55 to 125 Rating Space Supply current (max) (µA) 160
Technology family HC Number of channels 1 Operating temperature range (°C) -55 to 125 Rating Space Supply current (max) (µA) 160
CDIP (J) 16 135.3552 mm² (— mm × — mm) CFP (W) 16 69.319 mm² (— mm × — mm)
  • Targeted Specifically for High-Speed Memory Decoders and Data-Transmission Systems
  • Wide Operating Voltage Range (2 V to 6 V)
  • Outputs Can Drive Up To 10 LSTTL Loads
  • Low Power Consumption, 80-µA Maximum ICC
  • Typical tpd = 15 ns
  • ±4-mA Output Drive at 5 V
  • Low Input Current of 1-µA Maximum
  • Active Low Outputs ( Selected Output is Low)
  • Incorporate Three Enable Inputs to Simplify Cascading or Data Reception
  • Targeted Specifically for High-Speed Memory Decoders and Data-Transmission Systems
  • Wide Operating Voltage Range (2 V to 6 V)
  • Outputs Can Drive Up To 10 LSTTL Loads
  • Low Power Consumption, 80-µA Maximum ICC
  • Typical tpd = 15 ns
  • ±4-mA Output Drive at 5 V
  • Low Input Current of 1-µA Maximum
  • Active Low Outputs ( Selected Output is Low)
  • Incorporate Three Enable Inputs to Simplify Cascading or Data Reception

The SNx4HC138 devices are designed to be used in high-performance memory-decoding or data-routing applications requiring very short propagation delay times. In high-performance memory systems, these decoders can be used to minimize the effects of system decoding. When employed with high-speed memories using a fast enable circuit, the delay times of these decoders and the enable time of the memory are usually less than the typical access time of the memory. This means that the effective system delay introduced by the decoders is negligible.

The SNx4HC138 devices are designed to be used in high-performance memory-decoding or data-routing applications requiring very short propagation delay times. In high-performance memory systems, these decoders can be used to minimize the effects of system decoding. When employed with high-speed memories using a fast enable circuit, the delay times of these decoders and the enable time of the memory are usually less than the typical access time of the memory. This means that the effective system delay introduced by the decoders is negligible.
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Technical documentation

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Top documentation Type Title Format options Date
* Data sheet SNx4HC138 3-Line To 8-Line Decoders/Demultiplexers datasheet (Rev. G) PDF | HTML Oct 8, 2021
* SMD SN54HC138-SP SMD 5962-84062 Jul 8, 2016

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