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SN54HC590A

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8-Bit Binary Counters With 3-State Output Registers

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Data sheet

SN54HC590A

ACTIVE
Data sheet Order now

Product details

Function Counter Bits (#) 8 Technology family HC Input type Standard CMOS Output type 3-State Features Balanced outputs, High speed (tpd 10-50ns), Positive input clamp diode Operating temperature range (°C) -55 to 125 Rating Military
Function Counter Bits (#) 8 Technology family HC Input type Standard CMOS Output type 3-State Features Balanced outputs, High speed (tpd 10-50ns), Positive input clamp diode Operating temperature range (°C) -55 to 125 Rating Military
LCCC (FK) 20 79.0321 mm² (— mm × — mm) CDIP (J) 16 135.3552 mm² (— mm × — mm) CFP (W) 16 69.319 mm² (— mm × — mm)
  • 2-V to 6-V VCC Operation
  • High-Current 3-State Parallel Register Outputs Can Drive Up to 15 LSTTL Loads
  • Low Power Consumption, 80-µA Max ICC
  • Typical tpd = 14 ns
  • ±6-mA Output Drive at 5 V
  • Low Input Current of 1 µA Max
  • 8-Bit Counter With Register
  • Counter Has Direct Clear
  • 2-V to 6-V VCC Operation
  • High-Current 3-State Parallel Register Outputs Can Drive Up to 15 LSTTL Loads
  • Low Power Consumption, 80-µA Max ICC
  • Typical tpd = 14 ns
  • ±6-mA Output Drive at 5 V
  • Low Input Current of 1 µA Max
  • 8-Bit Counter With Register
  • Counter Has Direct Clear

The 'HC590A devices contain an 8-bit binary counter that feeds an 8-bit storage register. The storage register has parallel outputs. Separate clocks are provided for both the binary counter and storage register. The binary counter features direct clear (CCLR)\ and count-enable (CCKEN)\ inputs. A ripple-carry output (RCO)\ is provided for cascading. Expansion is accomplished easily for two stages by connecting RCO\ of the first stage to CCKEN\ of the second stage. Cascading for larger count chains can be accomplished by connecting RCO\ of each stage to the counter clock (CCLK) input of the following stage.

CCLK and the register clock (RCLK) inputs are positive-edge triggered. If both clocks are connected together, the counter state always is one count ahead of the register. Internal circuitry prevents clocking from the clock enable.

The 'HC590A devices contain an 8-bit binary counter that feeds an 8-bit storage register. The storage register has parallel outputs. Separate clocks are provided for both the binary counter and storage register. The binary counter features direct clear (CCLR)\ and count-enable (CCKEN)\ inputs. A ripple-carry output (RCO)\ is provided for cascading. Expansion is accomplished easily for two stages by connecting RCO\ of the first stage to CCKEN\ of the second stage. Cascading for larger count chains can be accomplished by connecting RCO\ of each stage to the counter clock (CCLK) input of the following stage.

CCLK and the register clock (RCLK) inputs are positive-edge triggered. If both clocks are connected together, the counter state always is one count ahead of the register. Internal circuitry prevents clocking from the clock enable.
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Top documentation Type Title Format options Date
* Data sheet SN54HC590A, SN74HC590A datasheet (Rev. F) Sep 15, 2003
* SMD SN54HC590A SMD 5962-89603 Jun 21, 2016

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